Programmable IC State Recovery Under Pipelined Clock Gating
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Solution Overview
Problem
Pipelined clock gating circuitry in programmable ICs introduces latency, causing the clock to continue operating for additional cycles after the decision to stop it, resulting in an inability to accurately observe the circuit design's state at the desired clock cycle.
Innovation Solution
A method involving a clock control module that pipelines a clock gating signal, stores configuration data specifying the operational state, and advances the clock to restore the exact operational state by loading the stored configuration data into configuration memory, accounting for the latency introduced by pipelining.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pipelined clock gating circuitry is used to control clock stopping, then clock control capability is improved, but latency is introduced causing the clock to continue operating for additional cycles
Solution Approach 1:
The patent captures the circuit state at an earlier time point before the pipelined clock gating signal completes its propagation. Configuration data is stored in non-configuration memory at a first simulation clock cycle, then later loaded at a second simulation clock cycle after accounting for the pipeline latency, thereby recovering the state that existed when the clock gating decision was made.
Solution Approach 2:
The patent creates a copy of the circuit configuration data and stores it in non-configuration memory. This copied data represents the circuit state at a specific simulation clock cycle and can be loaded back later to restore that state, effectively decoupling the state capture moment from the state restoration moment.
2Reliability
If configuration data is stored in non-configuration memory and loaded later, then the desired operational state can be restored, but additional clock cycles are required for data transfer
Solution Approach 1:
The configuration data is captured and stored in non-configuration memory at a first simulation clock cycle, preparing it for future restoration. This preliminary capture allows the system to later restore the exact state without recalculating or re-capturing it, saving time during the restoration phase.
Solution Approach 2:
The patent separates the configuration data storage from the main configuration memory by using non-configuration memory. This dimensional separation allows rapid loading of configuration data without interfering with the normal configuration memory operations, effectively parallelizing the data transfer path.
Data Source
AI summary
A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory. At a second simulation clock cycle, the clock of the circuit design can be gated. The stored configuration data can be loaded into configuration memory of the programmable IC, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle. The clock of the circuit design can be advanced a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle.