FPGA Control Unit for Parallel Processor Storage Access
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Solution Overview
Problem
In systems where multiple processors access a shared storage device, existing technologies result in significant waiting times due to exclusive control mechanisms that prevent concurrent access, leading to inefficiencies.
Innovation Solution
An information processing apparatus with a processing circuit that manages parallel access to storage areas by multiple processors, using a control unit to coordinate reading and updating data across different storage areas, allowing simultaneous access without interfering with ongoing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exclusive control is used to manage access to the storage device by multiple processors, then data access safety is ensured, but waiting time increases significantly
Solution Approach 1:
The storage device is divided into multiple independent storage areas (first storage area and second storage area), each accessible by different processors. This segmentation allows parallel access while maintaining data safety within each segment, resolving the contradiction between exclusive control reliability and access efficiency.
Solution Approach 2:
A control unit is introduced as an intermediary between processors and the storage device. The control unit manages access requests, determines whether to grant access based on current operations, and coordinates parallel access to different storage areas. This mediator enables safe concurrent access without requiring complete exclusive control, significantly reducing waiting time while maintaining data access safety.
2Reliability
If one processor occupies the storage device for exclusive access, then data consistency is maintained, but system productivity decreases
Solution Approach 1:
The storage device is segmented into multiple independent storage areas that can be accessed simultaneously by different processors. This allows the system to maintain data consistency within each storage area while enabling parallel operations across different areas, thereby improving overall system productivity without sacrificing data consistency.
Solution Approach 2:
The control unit dynamically determines whether to grant access to the storage device based on the current operational state. Instead of static exclusive control, the system adaptively manages access permissions, allowing parallel access when safe and maintaining exclusive control when necessary. This dynamic approach optimizes both data consistency and system efficiency.
3Speed
If parallel access is enabled for multiple processors to the storage device, then processing speed increases, but data access safety may be compromised
Solution Approach 1:
The storage device is divided into multiple independent storage areas, each with its own access control. This segmentation enables parallel access by different processors to different storage areas simultaneously, increasing processing speed while maintaining data access safety through isolated control of each segment.
Solution Approach 2:
The control unit acts as an intermediary that manages parallel access requests from multiple processors. It determines whether to grant access based on the current state of storage operations, ensuring that parallel access does not compromise data safety. This mediator enables safe concurrent access, achieving both high processing speed and data access reliability.
Data Source
AI summary
An information processing apparatus includes a main CPU storage area and a sub-CPU storage area. The information processing apparatus further includes an FPGA capable of processing access to the main CPU storage area by a main CPU and access to the sub-CPU storage area by a second CPU in parallel. The FPGA has an FPGA control unit that performs processing. The FPGA control unit is configured to read prescribed data from an SPI device to the main CPU storage area and the sub-CPU storage area, update the prescribed data of the sub-CPU storage area when receiving an updating request from the sub-CPU, and read the prescribed data of the main CPU storage area to the main CPU when receiving a reading request from the main CPU.