FPGA Non-Mounted Storage Test Device for SSD
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Solution Overview
Problem
Conventional SSD test devices face limitations in buffer capacity, leading to increased testing time due to either small buffer sizes requiring small data blocks or large buffer sizes that exceed system memory capabilities, and slower response times in non-mounted test environments.
Innovation Solution
A non-mounted storage test device based on FPGA, featuring a processor unit for enumeration and configuration of the PCIe bus tree, a device driver unit for ATA command generation, a data engine unit for pattern data generation, and a DMA driver/address translation unit for efficient data operations, allowing for rapid testing of large SSDs by optimizing buffer usage and reducing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the buffer capacity is increased to test large SSDs, then the testing performance is improved, but the system memory capacity requirement increases beyond available memory
Solution Approach 1:
The patent extracts the expected data buffer from the conventional test device architecture and replaces it with a pattern data generation unit that generates test patterns on-the-fly. This eliminates the need for large pre-stored expected data buffers while maintaining the ability to verify data integrity during SSD testing.
Solution Approach 2:
Instead of storing large volumes of expected data in buffers, the patent uses a pattern data generator that creates test patterns and compares read data against these generated patterns. This copying approach replaces physical buffer storage with computational pattern generation, reducing memory requirements while maintaining testing capability.
2Quantity of substance
If the buffer size is reduced to fit within system memory, then the memory requirement is satisfied, but the testing time increases due to smaller data blocks
Solution Approach 1:
The patent implements continuous data streaming through the PCIe bus between the test device and SSD, eliminating the need for discrete buffer-based data transfers. The pattern data generator continuously generates test patterns and the system continuously reads and compares data streams, maintaining constant useful action without buffer limitations.
Solution Approach 2:
The patent transitions from static buffer-based data handling to dynamic on-the-fly pattern generation. The pattern data generator dynamically creates test patterns during the testing process, allowing the system to adaptively handle data streams of any size without being constrained by fixed buffer capacities.
3Ease of operation
If a mounted test environment is used, then the test device can access storage resources, but the response time and test time are increased
Solution Approach 1:
The patent replaces the mechanical/mounted-based storage access mechanism with a direct PCIe bus-based data stream mechanism. Instead of relying on mounted storage access protocols that introduce overhead, the system uses direct PCIe transactions for data transfer, eliminating the time penalties associated with mounted system operations.
Solution Approach 2:
The patent segments the testing function into distinct modular units: a pattern data generator for creating test patterns, a reader for accessing SSD data, and a comparator for verification. This segmentation allows each component to operate independently and efficiently through PCIe, reducing the overall response time compared to integrated mounted systems.
Data Source
AI summary
A non-mounted storage test device based on FPGA includes a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.