FPGA Modular Implementation via Subsystem Equivalence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and size of circuit designs for field-programmable gate arrays (FPGAs) lead to exponential effort in prototype development, straining tool capacity and increasing complexity, with existing technologies struggling to efficiently process and implement large designs due to limited FPGA capacity and manual intervention requirements.
Innovation Solution
The method involves identifying equivalent subsystems within a circuit design, generating replicated subsystems to reduce the number of unique implementations, and using modular flow techniques to parallel process and reuse processing results, thereby reducing the number of FPGAs needed and streamlining the implementation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the circuit design size and complexity increase, then the functionality and capability of the FPGA system improve, but the prototype development effort and tool capacity strain increase exponentially
Solution Approach 1:
The circuit design is divided into multiple subsystems that can be independently analyzed for equivalence. The system segments the large design into manageable units, processes them in parallel, and combines results, thereby reducing the exponential development effort while maintaining full system capability.
Solution Approach 2:
The system identifies equivalent subsystems and creates replicated instances of them. Instead of processing each subsystem individually, equivalent subsystems are copied and processed together, significantly reducing the total processing effort and tool capacity requirements while preserving design functionality.
2Quantity of substance
If more FPGAs are used to implement larger circuit designs, then the design capacity increases, but the number of manual interventions and processing complexity increase
Solution Approach 1:
The equivalence analysis system performs multiple functions: it identifies equivalent subsystems, generates replication candidates, and processes multiple subsystems in parallel using a unified approach. This multi-functional system reduces processing complexity despite the increased number of FPGAs being implemented.
Solution Approach 2:
The system changes the processing parameters by analyzing subsystem equivalence and using replication candidates. This approach transforms the processing from handling each subsystem individually to processing replicated groups, reducing the effective complexity parameter even as the number of FPGAs increases.
3Loss of substance
If subsystem equivalence analysis is performed, then the number of replicated subsystems increases reducing FPGA count, but the analysis processing time and computational effort increase
Solution Approach 1:
The system performs preliminary equivalence analysis on subsystems before final implementation. By pre-identifying equivalent subsystems and creating replication candidates in advance, the system reduces the overall processing time and computational effort required during the implementation phase, even though analysis is performed upfront.
Data Source
AI summary
Certain aspects of the present disclosure are directed towards a method for circuit equivalence processing. The method generally includes: receiving a circuit design including a plurality of subsystems, each of the plurality of subsystems being implemented using at least one field-programmable gate array (FPGA); analyzing, via one or more processors, the plurality of subsystems for equivalence to identify at least two subsystems of the plurality of subsystems to be replaced with at least two replicated subsystems; and generating a netlist for the circuit design including the at least two replicated subsystems.