FPGA SV Data Reorganization for 32-bit DSP Addressing
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Solution Overview
Problem
Existing technologies using 8-bit addressing processors for ASN.1 decoding in smart substation process layers face inefficiencies due to insufficient data processing capabilities, leading to poor performance in handling high-frequency SV Ethernet data according to IEC61850-9-2 protocol.
Innovation Solution
A FPGA is used to reorganize SV data into 32-bit aligned format before processing by a high-performance DSP, aligning Ethernet frame headers and APDU according to ASN.1 coding rules, enabling direct 32-bit addressing and maximizing DSP performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an 8-bit addressing processor is used for ASN.1 decoding, then the device complexity is reduced, but the data processing capability and decoding efficiency are insufficient
Solution Approach 1:
The system is segmented into two parts: an 8-bit processor that handles protocol analysis and address generation, and a separate addressing processor that handles actual data access and decoding. This segmentation allows each component to be optimized for its specific function, maintaining low overall complexity while achieving high decoding efficiency through specialized hardware acceleration.
Solution Approach 2:
An intermediary addressing processor is introduced between the 8-bit main processor and the data memory. This intermediary component translates logical addresses generated by the 8-bit processor into physical memory addresses, enabling efficient data access without requiring the main processor to have complex addressing capabilities.
2Productivity
If a DSP with 32-bit addressing and large on-chip cache is used, then the data processing capability is improved, but the software complexity and decoding efficiency decline due to data splitting and reorganization requirements
Solution Approach 1:
The addressing processor performs preliminary actions by pre-calculating and pre-organizing data in 32-bit aligned format before the DSP needs to access it. This preliminary organization of data eliminates the need for complex software-based splitting and reorganization operations, allowing the DSP to directly process data in an optimized format.
Solution Approach 2:
The addressing processor serves itself by autonomously handling address translation and data organization tasks without requiring intervention from the main processor or DSP. This self-service capability reduces the software burden on the DSP and maintains high processing efficiency.
3Productivity
If data addresses are aligned as per 32-bit format with software-based splitting and reorganization, then the data processing ability is improved, but the decoding efficiency dramatically declines
Solution Approach 1:
The patent replaces the mechanical software-based data splitting and reorganization process with a hardware-based addressing processor that automatically performs address translation and data organization. This substitution eliminates the time-consuming software operations while maintaining 32-bit data alignment, thereby preserving high processing ability without the efficiency penalty.
Data Source
AI summary
This invention relates to a method for making 32-bit addressing of SV data by utilizing FPGA, which may be applied to processing digital sampling data in an equipment of an intelligent substation. Specifically, the method includes the following steps: FPGA receiving naked SV data packages generated based on IEEE802.3 standard; analyzing data structure of Ethernet frame; based on characteristics of the Ethernet frame of the SV data, the SV data of the network byte sequence being reorganized by utilizing ASN.1 coding rules, so that the SV data being converted into a data that can be directly accessed by 32-bit addressing processors. As a result, SV data decoding efficiency is improved greatly. This invention may make the decoding efficiency of 32-bit addressing processor improved by 5-10 times, thus solve problem of declined efficiency due to processing network byte order by splitting and reorganization.