FPGA Switch Block Leakage Reduction With Mixed-Threshold Transistors
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Solution Overview
Problem
FPGA architectures face significant challenges with high power consumption due to leakage current, especially as technology scales, which hampers their adoption in low-power portable environments and wireless applications, despite efforts like dual threshold approaches that affect timing performance.
Innovation Solution
The introduction of high-voltage transistors in switch blocks, combined with footer transistors and body biasing, reduces leakage current while maintaining timing performance, and the use of super cut-off techniques further minimizes power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high threshold transistors are used to reduce leakage current, then power consumption is reduced, but timing performance deteriorates due to increased delays
Solution Approach 1:
The patent applies different threshold voltage characteristics to different parts of the switch block circuit. Specifically, the pass-transistors use low threshold voltage for fast switching, while the buffer stage uses high threshold voltage transistors to reduce leakage. This local differentiation allows the circuit to achieve both fast timing performance and low power consumption by optimizing each region for its specific function.
2Loss of energy
If dual threshold approach is applied to reduce leakage, then static power consumption is reduced, but device complexity increases due to additional circuit elements
Solution Approach 1:
The patent combines the dual threshold approach with a buffer stage design that integrates the high threshold transistors into the existing switch block structure. The buffer stage merges the function of signal conditioning with leakage reduction, using high threshold transistors in series with the signal path to block leakage currents while maintaining the same external interface and control logic.
3Loss of energy
If high threshold transistors are used throughout the circuit, then leakage power is reduced by two orders of magnitude, but area occupation increases
Solution Approach 1:
The patent restricts the use of high threshold transistors to only the buffer stage portion of the switch block, while the pass-transistor switching elements continue to use low threshold transistors. This localized application of high threshold devices achieves significant leakage reduction without requiring the entire circuit to be redesigned with larger, high threshold transistors, thus minimizing area overhead.
Data Source
AI summary
A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.