FPGA Switch Block Segmentation for Gate Leakage Reduction
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) with cross-point switch blocks face issues of high power consumption due to gate leakage and challenges in testing and writing operations, particularly when using CMOS transistors and anti-fuse elements, which lead to increased area requirements and slower writing/erasing speeds compared to SRAM memories.
Innovation Solution
The integration of NAND gates and test circuits within the switch block configuration, replacing cutoff transistors with logic circuits, and using two-terminal switch elements to reduce power consumption and enable efficient testing by controlling write and select signals, thereby minimizing gate leakage and facilitating faster operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If cross-point switch blocks are used to enable all input terminals to connect to all output terminals, then wiring flexibility is improved, but power consumption increases due to gate leakage
Solution Approach 1:
The switch block is divided into multiple regions with different connection capabilities. Some switch elements provide full connectivity while others provide limited connectivity, allowing the system to achieve required wiring flexibility while minimizing the number of active transistor gates and reducing leakage power consumption.
Solution Approach 2:
Different regions of the switch block are assigned different connection qualities. Regions requiring full connectivity use complete cross-point switch elements, while regions with lower connectivity requirements use simplified switch elements with fewer transistor gates, thereby reducing overall gate leakage while maintaining necessary wiring flexibility.
2Stability of the object's composition
If anti-fuse elements are used for writing operations, then non-volatile storage is achieved, but writing and erasing speeds decrease compared to SRAM memories
Solution Approach 1:
The system performs preliminary configuration of switch elements before final operation. By pre-establishing connections and configurations in volatile memory during manufacturing or initialization, the system reduces the need for slow anti-fuse writing operations during normal use, thereby improving effective writing speed while maintaining non-volatile storage capabilities.
Solution Approach 2:
SRAM memory cells are used as intermediary storage elements that can be quickly written and read. These SRAM elements mediate between the fast read operations and the slow write operations of anti-fuse elements, allowing the system to achieve both non-volatile storage and fast writing speeds by using SRAM as a buffer during configuration updates.
3Device complexity
If cutoff transistors are used to control switch elements, then simple switching control is achieved, but testing and writing operations become difficult
Solution Approach 1:
The switch control circuit is designed to perform multiple functions including normal switching operation, testing, and writing operations. By integrating test and write capabilities into the same control structure used for normal switching, the system maintains simple control logic while enabling comprehensive testing and programming operations without requiring separate complex control paths.
Solution Approach 2:
The control circuit incorporates feedback mechanisms that monitor the state of switch elements and adjust control signals accordingly. This feedback enables the control circuit to distinguish between testing operations and normal switching operations, and to properly manage writing operations to anti-fuse elements, thereby simplifying the overall control structure while enabling complex operations.
Data Source
AI summary
An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.