FPGA Synthetic Instruments for High-Speed ATE Signal Integrity
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Solution Overview
Problem
Current automatic test equipment (ATE) struggles to effectively test high-speed integrated circuit bus structures due to limitations in applying and measuring signals at speeds greater than 1 Gbps, leading to challenges in diagnosing faults and failures, particularly with phase jitter, noise, and bit error rates, and is not adaptable to continuously evolving UUT technologies without significant upgrades or increased costs.
Innovation Solution
The implementation of reconfigurable synthetic instruments within a FPGA, which allows for the transmission and reception of high-speed signals, enabling testing beyond the original design capabilities of ATE, and facilitates the reuse of test programs and interfaces to accommodate various high-speed buses, including USB 3.0 and HDMI, by generating both 'good' and 'faulty' signals and compensating for signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ATE is used for high-speed testing, then device complexity is reduced, but measurement precision deteriorates at speeds greater than 1 Gbps
Solution Approach 1:
The patent implements dynamic reconfiguration of ATE instruments using FPGA technology, allowing the test equipment to adapt its architecture and measurement capabilities in real-time based on the specific high-speed bus protocol being tested. This enables precise measurement of signals at speeds greater than 1 Gbps by dynamically adjusting the instrument's internal logic and timing parameters.
Solution Approach 2:
The system changes key operational parameters such as clock frequency, data rate, and protocol-specific timing parameters to match the requirements of different high-speed buses. By dynamically adjusting these parameters, the ATE achieves accurate measurements at varying speeds while maintaining a relatively simple base hardware architecture.
2Adaptability or versatility
If ATE is upgraded to support new UUT technologies, then adaptability improves, but cost increases
Solution Approach 1:
The patent creates a universal ATE platform with reconfigurable instruments that can test multiple high-speed bus protocols (PCIe, USB 3.0, HDMI, SATA, SAS) using a single hardware architecture. The FPGA-based instruments can be programmed to support different protocols, eliminating the need for separate dedicated test equipment for each bus type and significantly reducing development costs.
Solution Approach 2:
The system uses software-based protocol implementations and virtual instrumentation approaches to replicate the functionality of expensive dedicated high-speed test equipment. By copying the essential measurement and control logic in software/FPGA rather than requiring dedicated hardware for each protocol, the system achieves broad adaptability at lower cost.
3Adaptability or versatility
If reconfigurable synthetic instruments are implemented, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent introduces an intermediate layer of protocol-specific software and configuration files that mediate between the user's testing requirements and the complex FPGA reconfiguration process. This intermediary software automatically generates the appropriate configuration bitstreams and control sequences, shielding users from the underlying complexity while enabling flexible adaptation to different high-speed protocols.
Data Source
AI summary
A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.