FPGA TDC Multiplexer Reconfiguration for Precise Timing

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Solution Overview

Problem

FPGAs face limitations in resolution and accuracy due to resource constraints, jitter, non-linear behavior, and routing delays, which affect the performance of Time-to-Digital Converters (TDCs) used in high-precision timing measurements.

Innovation Solution

An FPGA configuration that combines multiple TDCs with a multiplexer to selectively connect input signals, incorporates a calibration unit for averaging time differences, and includes a code conversion part to sort thermometer codes based on data path delay, enhancing accuracy and resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple TDCs are combined to improve measurement precision, then resolution and accuracy are improved, but device complexity increases

Engineering Contradiction:
ImproveTDC measurement precisionVSAvoidTDC device complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple TDCs are combined in parallel within the FPGA to improve measurement precision. The patent integrates several TDC units that can simultaneously process different signal pairs, allowing for statistical averaging and enhanced measurement accuracy while sharing common calibration and control resources

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The TDC system is designed with universal input node pairs that can be selectively connected to different signal sources through multiplexers. The same TDC hardware can measure multiple different signal pairs (e.g., start-stop, start-start, stop-stop) by reconfiguring the multiplexer connections, reducing the need for dedicated TDCs for each measurement type

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If FPGA routing resources are increased to reduce routing delays, then measurement accuracy is improved, but resource constraints are worsened

Engineering Contradiction:
ImproveTDC measurement accuracyVSAvoidFPGA resource usage
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The TDC input interface is segmented into separate input node pairs (e.g., S1+, S1-, S2+, S2-) that can be independently configured. This segmentation allows signals to be routed through dedicated paths while sharing common TDC resources, reducing the need for extensive point-to-point routing connections

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiplexers are introduced as intermediary components that selectively connect different signal pairs to the TDC input node pairs. This mediation allows multiple signal sources to share common routing paths to the TDC, reducing overall routing congestion and resource usage while maintaining measurement accuracy through controlled signal selection

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4672611A2TDC including multiplexer reconfiguring input signal, and FPGA including same
Publication Date: 2025.12.31 SDT INC
  • EP4672611A2 patent drawingFigure 1
  • EP4672611A2 patent drawingFigure 2
  • EP4672611A2 patent drawingFigure 3

AI summary

Disclosed is an FPGA programmed to include a plurality of TDCs, wherein each said TDC is configured to determine a time difference between the occurrences of two signals and has an input node pair for receiving said two signals, and a multiplexer configured to selectively connect a plurality of input signals to the input node pair of each of said TDCs.