Inter-FPGA Data Transmission via Time-Division Multiplexing
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Solution Overview
Problem
Interconnected field programmable gate arrays (FPGAs) face limitations in data transmission due to the number of inputs/outputs (IOs) and frequency compatibility, restricting overall performance during system development.
Innovation Solution
A method utilizing a first register device to latch and sort data into partial sets based on payload attributes and pointers, followed by transmission through a time-division multiplexing (TDM) interface to a second register device, allowing data to be output to a second FPGA operating at a different clock frequency, thereby separating clock domains and enabling optimized frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple FPGAs are interconnected to perform different partitions in a system, then system functionality is improved, but the number of IOs becomes a limitation and device complexity increases
Solution Approach 1:
The patent merges multiple data transmission channels into a single TDM interface. Multiple sets of data (payloads and pointers) that would traditionally require separate IO connections are combined into one shared communication path, allowing inter-FPGA communication while reducing the total number of physical IOs required.
Solution Approach 2:
The TDM interface serves multiple functions simultaneously - it transmits both payloads and pointers, handles multiple data sets from different FPGAs, and operates across different clock domains. This multi-functional interface replaces what would traditionally require multiple dedicated connections.
2Reliability
If interconnected FPGAs accommodate each other's frequency, then connectivity is maintained, but each FPGA cannot operate under its own optimized frequency, reducing overall performance
Solution Approach 1:
The TDM interface acts as an intermediary between FPGAs operating at different frequencies. It captures data from the first FPGA at its clock frequency, stores it in register devices, and transmits it at a separate TDM clock frequency to the second FPGA. This mediator approach allows each FPGA to operate independently at its optimized frequency while maintaining reliable communication.
Solution Approach 2:
The patent segments the data transmission process into distinct stages: data capture at the first FPGA's clock frequency, intermediate storage in register devices, and transmission at the TDM clock frequency. This segmentation allows frequency decoupling between interconnected FPGAs, enabling each to operate at its optimized frequency without compromising connectivity.
3Productivity
If data is transmitted between FPGAs operating at different frequencies, then frequency optimization is achieved, but data transmission control complexity increases
Solution Approach 1:
The TDM interface employs periodic action by transmitting data in structured time slots according to a TDM clock. Data sets are transmitted in a repeating sequence at regular intervals, which simplifies the control logic compared to arbitrary timing schemes. This periodic transmission pattern makes frequency translation more manageable despite the complexity of operating across different clock domains.
Data Source
AI summary
A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.