FPGA Test Channel Reduction via Daisy-Chain Register Segmentation
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Solution Overview
Problem
The existing methods for testing field programmable gate arrays (FPGAs) require a one-to-one correspondence between input/output blocks (IOBs) and test channels, leading to a shortage of test channels when testing multiple FPGAs simultaneously, limiting the ability to test multiple integrated circuits simultaneously with the same automated test equipment (ATE).
Innovation Solution
The system configures a daisy-chain of registers in a closed input/output loop, where a set signal and clock signal are used to circulate logic states around the loop, allowing multiple IOBs to share a single test channel by selectively placing output blocks in an output mode only when a specific logic state is registered, thereby reducing the number of required test channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If one IOB is assigned to one test channel for one-to-one correspondence, then testing accuracy is improved, but test channel availability deteriorates
Solution Approach 1:
The patent segments the testing process by dividing multiple IOBs into groups that share common nodes. Instead of dedicating one test channel per IOB, multiple IOBs are segmented to share test channels through common nodes, reducing the total number of test channels needed while maintaining testing accuracy through selective activation.
Solution Approach 2:
The patent implements periodic action through sequential activation of tri-state buffers. Each tri-state buffer is activated in sequence during different time periods, allowing multiple IOBs to share test channels periodically. This ensures that at any given moment, only one IOB per common node is active, maintaining testing accuracy while improving channel availability.
2Productivity
If multiple FPGAs are tested simultaneously, then productivity is improved, but test channel demand increases
Solution Approach 1:
The patent makes test channels universal by enabling them to serve multiple IOBs across different FPGAs. Through common nodes and sequential activation, a single test channel can be shared by multiple IOBs in different FPGAs, allowing simultaneous testing of multiple devices without proportionally increasing test channel demand.
Solution Approach 2:
The patent merges multiple IOBs and test channels through common nodes. By combining the test paths of multiple IOBs that share common nodes, the system reduces the total number of test channels required for simultaneous multi-FPGA testing, thereby improving productivity without linearly increasing channel demand.
3Quantity of substance
If multiple IOBs share a single test channel, then test channel availability is improved, but device complexity increases
Solution Approach 1:
The patent introduces tri-state buffers as intermediary components between IOBs and test channels. These buffers act as mediators that control signal flow, enabling multiple IOBs to share test channels through common nodes. The tri-state buffers manage the complexity by providing a standardized interface and control mechanism, isolating the complexity from the overall system architecture.
Data Source
AI summary
Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1 through 310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (210-1 through 210-N) is controlled responsive to a series of outputs (316-1 through 316-N) provided from a portion of the daisy-chain of registers (310-1 through 310-N) to selectively place an output block of output blocks (210-1 through 210-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (210-1 through 210-N) are commonly coupled at an output node (212) for coupling to a single test channel, as only one output block is in the output mode at a time.