FPGA Logic Tile Test Circuitry for Parallel Isolated Testing
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Solution Overview
Problem
Current methods for testing logic tiles in integrated circuits are inefficient, as they often require serial testing and do not effectively isolate the circuitry of each tile from others, making it difficult to determine the integrity and operability of individual tiles.
Innovation Solution
The implementation of parallel testing techniques and isolation circuitry allows for the simultaneous testing of multiple logic tiles, with the ability to disconnect each tile's interconnect network from others during testing, enabling the assessment of each tile's functionality independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If serial testing methods are used for logic tiles, then testing can be performed with simple circuitry, but test time and productivity are significantly increased
Solution Approach 1:
The patent divides the logic tile array into multiple independently testable segments by introducing isolation circuitry. Each logic tile can be electrically isolated from others during testing, allowing parallel test operations on multiple tiles simultaneously. This segmentation enables the transition from serial to parallel testing, directly reducing test time while maintaining testing completeness.
Solution Approach 2:
The patent introduces a temporal dimension to testing by enabling parallel execution of test sequences across multiple logic tiles. Instead of testing tiles sequentially in time, the isolation circuitry allows simultaneous testing of multiple tiles, effectively adding a parallel execution dimension to the testing process and dramatically improving productivity.
2Measurement precision
If isolation circuitry is implemented to disconnect logic tile interconnect networks, then individual tile integrity can be accurately assessed, but device complexity increases
Solution Approach 1:
The patent extracts the interconnect network connections from the logic tiles during testing by implementing isolation circuitry. This extraction allows each logic tile to be tested independently without interference from adjacent tiles, ensuring accurate measurement of individual tile integrity. The isolation is temporary and only active during test modes, maintaining normal operation during functional modes.
Solution Approach 2:
The patent introduces isolation circuitry as an intermediary element between logic tiles and their interconnect networks. This intermediary component controls the electrical connection state, allowing the tile to be connected during normal operation and disconnected during testing. The mediator enables precise measurement by controlling when isolation occurs without permanently altering the tile structure.
3Productivity
If parallel testing of multiple logic tiles is performed, then productivity and test coverage are improved, but the complexity of test control circuitry increases
Solution Approach 1:
The patent merges the testing resources and control mechanisms across multiple logic tiles by implementing a unified parallel testing architecture. Instead of requiring separate test equipment for each tile, the isolation circuitry enables multiple tiles to share common test resources simultaneously. This merging approach improves productivity while keeping control complexity manageable through resource sharing.
Data Source
AI summary
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.