FPGA Logic Tile Test Circuitry for Parallel Isolation Testing
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Solution Overview
Problem
Current methods for testing logic tiles in field programmable gate arrays (FPGAs) are inefficient, as they often require serial testing and do not allow for effective isolation of circuitry, making it difficult to determine the integrity and operability of individual tiles without interference from adjacent or external circuitry.
Innovation Solution
The implementation of parallel testing techniques and isolation circuitry that enables each logic tile to be tested concurrently, with the ability to disconnect its interconnect network and I/Os from other tiles during testing, allowing for independent assessment of each tile's functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial testing is used for logic tiles, then testing can be performed with simple circuitry, but test time is excessive and productivity is low
Solution Approach 1:
The patent divides the FPGA into multiple logic tiles, each with its own isolated interconnect network and test circuitry. This segmentation enables parallel testing of multiple tiles simultaneously, dramatically reducing test time while maintaining manageable circuitry complexity through modular organization
Solution Approach 2:
The patent combines multiple test operations into a unified parallel testing framework where multiple logic tiles are tested concurrently using shared test resources and coordinated control signals, improving productivity without proportionally increasing overall system complexity
2Measurement precision
If logic tiles are tested in isolation, then measurement precision of individual tile integrity is improved, but device complexity increases due to isolation circuitry
Solution Approach 1:
The patent extracts the interconnect network from the logic tile core, allowing the interconnect to be independently tested. The interconnect network can be disconnected and tested separately from the logic tile, enabling precise measurement of interconnect integrity without interference from logic tile operations
Solution Approach 2:
The patent introduces isolation circuitry as an intermediary between logic tiles during testing. This intermediary enables controlled connection and disconnection of tiles, allowing precise measurement of individual tile integrity while managing the complexity through standardized isolation interfaces
3Productivity
If parallel testing is implemented, then productivity and test coverage are improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent designs test circuitry with universal functionality that can test multiple logic tiles using the same test resources and procedures. The isolated interconnect network and test logic can be replicated across tiles, allowing parallel testing without proportionally increasing resource requirements
Solution Approach 2:
The patent transitions from serial testing (one-dimensional sequential process) to parallel testing (multi-dimensional concurrent process). By utilizing the spatial dimension of multiple tiles testing simultaneously, productivity is dramatically improved while managing complexity through synchronized control
Data Source
AI summary
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.