Multi-Die FPGA Interconnect Time Multiplexing
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Solution Overview
Problem
The limited number of inter-die connections in multi-die FPGAs hinders the efficient mapping of highly connected sub-circuits, leading to compilation stalls and increased hardware costs when trying to reduce sub-circuit sizes or extend compilation times through iterative partitioning.
Innovation Solution
Implement time multiplexing on inter-die connections by using multiplexers and de-multiplexers synchronized with a clock signal, and inserting pipeline registers to break long routing paths, allowing multiple logical signals to be transmitted over a single physical connection without reducing sub-circuit sizes or increasing hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of inter-die connections is increased to map highly connected sub-circuits, then the mapping capability is improved, but the hardware cost and device complexity increase
Solution Approach 1:
The patent applies time-division multiplexing to inter-die connections, where multiple logical signals are transmitted periodically over a single physical connection by allocating different time slots to different signals. This periodic action allows the same physical connection to serve multiple logical purposes sequentially, thereby improving mapping capability without increasing the number of physical connections or hardware complexity
2Reliability
If iterative partitioning is performed to reduce inter-die connections, then the compilation success rate is improved, but the compilation time increases significantly
Solution Approach 1:
The patent performs preliminary analysis of the circuit design to identify highly connected sub-circuits before compilation. By pre-determining which sub-circuits require time-division multiplexing and configuring the appropriate number of multiplexers and de-multiplexers in advance, the system avoids iterative partitioning attempts during compilation. This preliminary action ensures compilation success while minimizing compilation time, as no iterative retries are needed
3Productivity
If sub-circuit sizes are reduced to optimize FPGA mapping, then the mapping efficiency is improved, but the number of FPGAs required increases, leading to increased hardware cost
Solution Approach 1:
The patent merges multiple logical connections between dies into a single shared physical connection by implementing time-division multiplexing at the inter-die interface. Multiplexers on the transmitting die and de-multiplexers on the receiving die allow multiple logical signals to share the same physical bandwidth. This merging approach maintains mapping efficiency for large sub-circuits while reducing the total number of FPGAs needed, as it maximizes the utilization of available inter-die connections
Data Source
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AI summary
A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.