FPGA Digital Circuit for External Timing Device Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test and measurement equipment for telecommunication systems face issues with detecting the presence and quality of external timing devices due to incorrect frequencies, improper connections, or noise interference, leading to erroneous results.
Innovation Solution
A digital circuit system is implemented within a field-programmable gate array (FPGA) that includes an oscillator, edge detector, binary counters, and a subtractor to accurately determine the presence and quality of an external timing device by distinguishing between driven and undriven signals without averaging noise, thus reducing false detections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock identification techniques count edges within a defined time period to estimate clock input frequency, then frequency estimation is achieved, but Gaussian noise is averaged out leading to false detection of clock even when input timing frequency signal is undriven
Solution Approach 1:
The patent segments the detection process into multiple independent measurements taken at different time instances rather than averaging all edges over a long period. By dividing the detection into discrete time segments and comparing individual measurements, the system can identify genuine clock signals while rejecting noise that doesn't exhibit consistent periodic behavior across segments.
Solution Approach 2:
The patent employs periodic sampling and measurement at defined time intervals to detect clock signals. By taking measurements at regular periods and comparing them, the system can distinguish true periodic clock signals from random noise, as genuine clocks will show consistent periodic patterns across multiple measurement cycles while noise will not.
2Reliability
If additional hardware modifications are implemented to improve detection accuracy, then detection reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent implements a self-service detection mechanism where the FPGA uses its existing internal resources (timers, counters, and logic elements) to perform detection functions without requiring external hardware modifications. The detection algorithm leverages the FPGA's native capabilities to analyze timing signals, making the system self-sufficient and avoiding additional hardware complexity.
Solution Approach 2:
The patent makes the FPGA perform multiple functions using the same hardware resources - the device can both implement detection algorithms and execute telecommunication functions simultaneously. By programming the FPGA to handle detection tasks through software/firmware, the same hardware infrastructure serves dual purposes, eliminating the need for dedicated detection hardware.
Data Source
AI summary
A system for determine presence or quality of an external timing device is provided. The system may include a circuit (e.g., in a field-programmable gate array (FPGA)) having an input, an oscillator, an edge detector, a bit counter, and a calculator element. In some examples, the input may receive an input signal under test. The oscillator may advance a timer at a known rate to facilitate generation of clock samples for the input signal under test. The edge detector may measure edges of the input signal under test based on the clock samples. The circuit may include at least one bit counter to store a count associated with the measured edges for a shorter interval timer period and a longer interval timer period. The calculator element may determine presence or quality of an external timing device based on the count.