FPGA Timing Violation Detection via Logic Reprogramming
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Solution Overview
Problem
Hardware emulation systems face challenges in detecting timing violations due to non-deterministic behavior and the insertion of additional hardware, which can affect emulation capacity and fail to check timing validity exhaustively.
Innovation Solution
A method involving determining timing relationships between clocks, reconfiguring combinational logic as buffers, setting delays, and reprogramming clocks to detect timing violations by ensuring changes in flip-flop outputs are stored within a specific delay, using FPGA reprogramming and automatic test pattern generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional hardware is inserted to check signal stability during setup time, then timing violation detection capability is improved, but emulation capacity is reduced
Solution Approach 1:
The system uses the existing emulation hardware resources to perform both emulation and timing verification functions. The FPGA reconfigures the combinational logic between sequential elements to serve dual purposes: normal circuit operation and timing path verification, eliminating the need for separate dedicated verification hardware.
Solution Approach 2:
The emulation hardware is designed to perform multiple functions: it executes the circuit under test and simultaneously verifies timing constraints. The same FPGA resources that emulate the target circuit are reused for timing verification by reconfiguring logic elements as verification logic when needed.
2Reliability
If additional hardware is inserted to monitor emulation correctness, then timing violation detection is improved, but device complexity increases
Solution Approach 1:
The verification system is self-contained within the existing emulation architecture. The FPGA reconfigures its own logic elements to create verification paths without requiring external monitoring hardware or complex instrumentation interfaces.
Solution Approach 2:
The timing verification functionality is merged with the emulation functionality. The same hardware resources that implement the circuit under test are also used to implement the verification logic, combining multiple functions into a single integrated system.
3Measurement precision
If additional hardware is inserted to check timing validity, then measurement precision is improved, but loss of time increases due to more tests needed
Solution Approach 1:
The timing verification is performed continuously during normal emulation operation. The system monitors timing constraints in real-time as the circuit operates, rather than requiring separate discrete test sequences, thus maintaining continuous verification without interrupting the emulation flow.
Solution Approach 2:
The system automatically performs timing verification as part of its normal operation. The FPGA reconfigures logic to monitor timing paths and detect violations autonomously during emulation, eliminating the need for manual test setup and execution.
4Adaptability or versatility
If FPGA reprogramming is used to reconfigure combinational logic as buffers, then adaptability is improved, but device complexity increases
Solution Approach 1:
The system dynamically reconfigures the FPGA logic elements based on the verification needs. The combinational logic between sequential elements is reconfigured as buffers during timing verification phases and returns to its original function during normal emulation, providing dynamic adaptability.
Solution Approach 2:
The FPGA performs self-reconfiguration to enable timing verification. The device reprograms its own logic elements to create verification paths and then reprograms them back to their original configuration, eliminating the need for external reconfiguration control complexity.
Data Source
AI summary
A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.