FPGA Radiation Protection via Zone-Based TMR Placement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FPGAs in radiation environments suffer from single event upsets (SEUs) and multiple bit upsets (MBUs) due to natural radiation, with existing solutions either reducing performance, being costly, or requiring complex and resource-intensive implementations.
Innovation Solution
A protection method that subdivides the FPGA surface into zones and uses constraining signals to force placement and routing of replicated logic modules into distinct zones, ensuring that each TMR cell is physically separated, thereby reducing the risk of MBUs without compromising performance or increasing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If triplicated bistables (TMR) are placed close together for timing optimization, then timing performance is improved, but susceptibility to multiple bit upsets (MBUs) increases
Solution Approach 1:
The FPGA surface is segmented into multiple zones, and the placement tool is configured to place triplicated bistables of each TMR cell into different zones. This spatial segmentation ensures that particles affecting a single zone cannot corrupt all three bistables simultaneously, thereby maintaining both timing performance and reliability.
Solution Approach 2:
The patent applies different placement constraints to different regions of the FPGA by defining zones with specific characteristics. Each TMR cell's bistables are assigned to different zones with appropriate spacing, creating local quality variations that protect against MBUs while maintaining overall timing performance.
2Reliability
If coarser etching is used to increase bistable spacing, then resistance to MBUs is improved, but FPGA speed decreases
Solution Approach 1:
Instead of increasing physical spacing through coarser etching (one-dimensional solution), the patent uses software-based zone definitions to create logical separation in the placement space. This allows maintaining fine etching for speed while achieving effective spacing through multi-dimensional zone management.
Solution Approach 2:
The patent changes the placement parameters by defining zone boundaries and constraints rather than altering the physical etching parameters. This allows optimizing both speed (fine etching) and reliability (effective spacing) by controlling logical placement parameters instead of physical manufacturing parameters.
3Reliability
If individual submodules are triplicated and physically separated, then protection against MBUs is improved, but logic resource consumption increases significantly
Solution Approach 1:
The patent segments only the critical bistable elements for triplication within TMR cells, rather than triplicating entire submodules. This selective segmentation of bistables reduces logic resource consumption while maintaining protection against MBUs through zone-based spatial separation.
Solution Approach 2:
The patent applies triplication only to the necessary bistable elements rather than entire submodules, representing a partial action approach. This reduces the excessive logic resource consumption that would result from full submodule triplication while maintaining sufficient protection against MBUs.
Data Source
AI summary
A protection method for protecting an FPGA against natural radiation, the method comprising the steps of: defining at least one category of constraining signals defined so that a predetermined placement and routing tool cannot route more than a determined maximum number of different constraining signals to any one zone of the surface of the FPGA; replicating an initial logic module in order to obtain a plurality of replicated logic modules forming a replicated logic cell; and associating constraining signals with the replicated logic modules in such a manner that the number of constraining signals associated with the replicated logic cell is greater than a determined maximum number in order to force the placement and routing tool to place the replicated logic modules of the replicated logic cell in distinct zones of the surface of the FPGA.