FPGA User Traffic Generation via SRAM DRAM Segmentation
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Solution Overview
Problem
Current network testing methods using FPGA dedicated hardware are limited by SRAM space, preventing the generation of a large quantity of user packets at line rate.
Innovation Solution
A user traffic generation method and apparatus that utilizes a prefetch operation and cache operation between on-chip SRAM and DRAM to store and generate a mass of user packets, allowing for line-rate traffic generation by storing index information in SRAM and packets in DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If FPGA dedicated hardware with on-chip SRAM is used to generate user traffic, then precise control and ultrafast broadband traffic generation can be implemented, but the quantity of user packets is limited by SRAM space and cannot generate traffic at line rate
Solution Approach 1:
The patent divides the storage system into two segments: on-chip SRAM for storing index information and off-chip DRAM for storing actual user packets. This segmentation allows the system to leverage the fast access speed of SRAM for control operations while using the large capacity of DRAM to store mass user packets, thereby resolving the contradiction between precise control and packet quantity.
Solution Approach 2:
The patent introduces an intermediary mechanism (index information stored in SRAM) that bridges the fast access requirements and large storage needs. The index acts as a mediator that enables quick retrieval of packet locations without requiring the entire packet data to reside in fast SRAM memory, thus allowing both precise control and large packet quantities.
2Speed
If on-chip SRAM is used to store user packet header information, then fast access and precise control are achieved, but storage of a mass of user packets cannot be implemented
Solution Approach 1:
The patent segments the storage architecture into fast on-chip SRAM for index information and high-capacity off-chip DRAM for user packets. This allows the system to maintain fast access speeds through SRAM while achieving mass storage capability through DRAM, directly resolving the speed-capacity contradiction.
Solution Approach 2:
The patent creates a simplified copy (index information) of the packet data characteristics in SRAM that contains only the essential addressing information needed for fast access, while the full packet data resides in DRAM. This copying approach enables fast access without duplicating the entire packet content in fast memory.
3Speed
If SRAM space is used to store user packet data, then fast access is achieved, but the quantity of stored packets is limited and line rate generation cannot be achieved
Solution Approach 1:
The patent segments storage functionality between SRAM (for fast index access) and DRAM (for bulk packet storage), enabling the system to achieve both high-speed access characteristics and large-scale packet storage capacity necessary for line rate traffic generation.
Solution Approach 2:
The patent transitions from a single-dimension storage approach (everything in SRAM) to a two-dimensional storage hierarchy (SRAM for indices, DRAM for data). This dimensional change in the storage architecture allows simultaneous optimization of both access speed and storage capacity.
Data Source
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AI summary
Embodiments of the present invention disclose a user traffic generation method and apparatus. The method includes: receiving a user traffic generation instruction; performing, according to the user traffic generation instruction and index information pre-stored in a first on-chip static random access memory SRAM of a field programmable gate array FPGA, a prefetch operation and a cache operation on a user packet that is stored in a dynamic random access memory DRAM and indicated by the index information, where the first on-chip SRAM is configured to store index information of all user packets that need to be used, and the DRAM is configured to store all the user packets; and generating user traffic according to a user packet that is cached during the cache operation. According to the embodiments of the present invention, storage of a mass of user packets can be implemented, and user traffic can be generated at a line rate.