FPGA Transaction Data Encryption Parallel Processing
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Solution Overview
Problem
Existing data encryption methods using central processing units (CPUs) are vulnerable as they require transmitting encryption keys over communication networks and can only process data serially, which is inefficient and insecure.
Innovation Solution
A system utilizing a field programmable gate array (FPGA) device to encrypt and decrypt transaction data records, where the FPGA is coupled to a host application processor via a communication bus, allowing for parallel processing and storing encryption keys locally within the FPGA's read-only memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption keys are transmitted over communication networks to host computing devices, then encryption operations can be performed, but security is compromised due to vulnerability of key transmission
Solution Approach 1:
The encryption key management function is extracted from the host computing device and relocated to a dedicated security module or remote key management system. This separation allows the host to perform encryption operations without directly handling or transmitting keys over networks, thereby maintaining security while enabling encryption functionality.
Solution Approach 2:
A dedicated security module or remote key management system acts as an intermediary between the host computing device and the encryption keys. This intermediary handles key storage, retrieval, and distribution securely, eliminating the need for the host to transmit keys over networks while still enabling encryption operations.
2Productivity
If data is processed serially by CPU during ETL operations, then processing can be completed, but processing time is excessive
Solution Approach 1:
The data processing workflow is segmented into distinct stages: data extraction, parallel transformation operations, and data loading. By dividing the ETL process into separate modular components, different stages can be executed concurrently or in optimized sequences, significantly reducing overall processing time compared to purely serial CPU execution.
Solution Approach 2:
The patent transitions from single-threaded serial processing to multi-threaded parallel processing by utilizing multiple CPU cores or processing units simultaneously. This dimensional change from one-dimensional sequential execution to multi-dimensional parallel execution dramatically increases data processing throughput and reduces processing time.
Data Source
AI summary
Provided is a system including at least one host application processor and at least one field programmable gate array (FPGA) device coupled to the at least one host application processor via a communication bus, the at least one host application processor is programmed or configured to receive a transaction data record comprising transaction data associated with a payment transaction, transmit the transaction data record to the at least one FPGA device via the communication bus, and receive an encrypted transaction data record from the at least one FPGA device via the communication bus, wherein one or more data fields of the transaction data record are encrypted to generate the encrypted transaction data record. A method and computer program product are also provided.