Programmable IC Underlay Mapping for Faster FPGA Routing
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Solution Overview
Problem
Programmable integrated circuits, such as PLDs, often operate at significantly lower speeds than their maximum capability due to inefficient routing patterns, resulting in underutilization and prolonged compile times.
Innovation Solution
The method involves extracting and mapping user applications to 'fast routing patterns' or 'underlays' within the programmable integrated circuit interconnect architecture, which are optimized for specific logic utilization and speed, allowing for repeated patterns across the circuit to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional routing patterns are used in programmable integrated circuits, then the circuit can be configured flexibly, but the operating speed is limited to 300-400 MHz instead of reaching the maximum 1 GHz capability
Solution Approach 1:
The routing network is segmented into reusable underlay patterns (such as 2:1 multiplexer patterns, adder patterns, and function block patterns) that can be independently extracted and then composed to form complete routing solutions. This segmentation allows the routing problem to be broken down into manageable, pre-optimized components that can be assembled efficiently.
Solution Approach 2:
Underlay patterns are extracted and prepared in advance from the routing network architecture before actual circuit routing is performed. These pre-extracted patterns contain optimized routing paths that have been predetermined to meet specific timing and performance requirements, eliminating the need to perform complex routing optimization during the actual circuit compilation process.
2Productivity
If efficient routing patterns are extracted and used, then user application speed increases by up to two times, but the process of extracting and mapping underlays adds complexity to the design flow
Solution Approach 1:
The underlay extraction process is performed automatically by the compilation tool based on the target logic utilization and speed requirements. The tool self-configures the appropriate underlay patterns without requiring manual intervention from the designer, and the extracted underlays are automatically mapped to the user application during the compilation process.
Solution Approach 2:
The extracted underlay patterns are designed to be universal and reusable across different user applications and design scenarios. The same underlay patterns (such as 2:1 multiplexer patterns or adder patterns) can be applied to various different circuits and functions, making the complex extraction process pay off through repeated utilization across multiple designs.
3Loss of time
If underlays are extracted based on target logic utilization and speed, then compile times are reduced by 50% or more, but the routing network analysis requires sophisticated processing
Solution Approach 1:
The routing network analysis is segmented into distinct pattern types (multiplexer patterns, adder patterns, function block patterns) that can be independently extracted and analyzed. This segmentation allows the complex analysis to be divided into smaller, more manageable tasks that can be processed efficiently and parallelized.
Solution Approach 2:
Once underlay patterns are extracted from the routing network, they are copied and reused multiple times across different regions of the programmable logic device. The extraction process needs to be performed only once for each pattern type, and then the extracted patterns are replicated throughout the device, significantly reducing the overall compilation time while distributing the analysis workload.
Data Source
AI summary
A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.