Storage Controller FPGA Update via Main and Sideband Interfaces
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Solution Overview
Problem
Existing semiconductor devices face challenges in upgrading their controller functions due to the difficulty in modifying hardware modules, leading to increased costs and chip size when using separate dedicated circuits for receiving FPGA images.
Innovation Solution
A storage device with a nonvolatile memory and a controller, including a field programmable gate array (FPGA), receives and stores FPGA images through a main interface or sideband interface, allowing for updates without the need for a separate dedicated circuit, utilizing existing interfaces for efficient FPGA updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate dedicated circuit is used to receive FPGA images from external memory, then the FPGA update function is achieved, but the manufacturing cost increases and chip size increases
Solution Approach 1:
The patent applies universality by making the existing main interface and sideband interface capable of handling both their original functions and FPGA image reception. The controller's existing interfaces are enhanced to serve dual purposes: normal data communication and FPGA programming, eliminating the need for dedicated separate circuits and reducing overall device complexity
Solution Approach 2:
The patent merges the FPGA image reception function with the existing main interface and sideband interface circuits. Instead of adding separate dedicated hardware for receiving FPGA images from external memory, the invention combines this functionality into the existing interface structure, thereby reducing chip area and manufacturing complexity
2Adaptability or versatility
If a separate dedicated circuit is used to receive FPGA images from external memory, then the FPGA update function is achieved, but the manufacturing cost increases
Solution Approach 1:
The patent applies universality by making the existing main interface and sideband interface capable of handling both their original functions and FPGA image reception. The controller's existing interfaces are enhanced to serve dual purposes: normal data communication and FPGA programming, eliminating the need for dedicated separate circuits and reducing overall device complexity
Solution Approach 2:
The patent merges the FPGA image reception function with the existing main interface and sideband interface circuits. Instead of adding separate dedicated hardware for receiving FPGA images from external memory, the invention combines this functionality into the existing interface structure, thereby reducing chip area and manufacturing complexity
3Adaptability or versatility
If hardware modules in the controller are upgraded, then the controller function is improved, but it becomes difficult to upgrade after supply to end user
Solution Approach 1:
The patent applies dynamics by implementing a reconfigurable controller architecture where the FPGA portion can be dynamically updated through the existing interfaces. This allows the controller to transition from a static hardware module to a dynamic, upgradable system that can receive new functionality via FPGA images without requiring physical hardware changes or complex reconfiguration processes
Solution Approach 2:
The patent uses the FPGA as an intermediary layer between the fixed ASIC hardware and the desired functionality. The FPGA receives control signals and data through the existing main and sideband interfaces, processes them, and configures the hardware resources accordingly. This intermediary approach enables flexible upgrades without directly modifying the original hardware modules
Data Source
AI summary
A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.