FPGA User Clock Generation With PLLs for Multi-Chip Prototyping
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Solution Overview
Problem
Current FPGA prototyping systems face challenges in generating user clocks that match the high frequencies of modern circuit designs due to limited I/O pins and the inability of FPGAs to operate at the intended clock speeds, leading to reduced performance and accuracy in prototyping.
Innovation Solution
A method and apparatus for generating user clocks using a clock generation circuit with programmable logic devices, including phase-locked loops, to scale reference frequencies and produce user clock frequencies within each FPGA, reducing the need for multiple clock lines and maintaining phase relationships across FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple FPGAs are used for prototyping to overcome logic capacity limitations, then the logical capacity is sufficient, but the number of I/O pins required increases significantly
Solution Approach 1:
The patent combines multiple clock generation functions into a single reference clock input per FPGA. Instead of requiring separate clock inputs for each clock domain, the system uses one reference clock and generates all required user clocks internally through phase-locked loops and frequency synthesis, reducing I/O pin requirements while maintaining sufficient logical capacity across multiple FPGAs
2Device complexity
If FPGAs are used to generate user clocks at high frequencies, then I/O pin usage is reduced, but the FPGAs cannot operate at the intended clock speeds of modern circuit designs
Solution Approach 1:
The patent changes the frequency parameter of the reference clock dynamically. By using frequency synthesis techniques including phase-locked loops and programmable frequency dividers, the system can generate user clocks at various frequencies from a single reference clock source, allowing FPGAs to operate at reduced clock speeds while still generating high-frequency clocks for the circuit design under test
3Measurement precision
If multiple clock lines are provided to each FPGA to match modern circuit design frequencies, then the clock accuracy is improved, but the limited number of I/O pins is exceeded
Solution Approach 1:
The patent makes a single reference clock input serve multiple functions by using it to generate all required user clocks for different clock domains within the FPGA. This multi-functional approach allows the system to maintain accurate clock relationships across multiple frequencies without requiring separate physical clock lines for each frequency, thus preserving clock accuracy while minimizing I/O pin usage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more accurate and efficient prototyping by generating user clocks within each FPGA from a single reference clock, reducing I/O pin usage and maintaining clock phase relationships, thereby improving the speed and accuracy of circuit design verification.
Implementation Method 1
a first phase-locked loop to multiply a frequency of the reference clock to effectuate generation of a first multiplied clock
Implementation Method 2
a first frequency divider to divide the frequency of the first multiplied clock to effectuate generation of the first user clock having the first user clock frequency
Data Source
AI summary
A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.