FPGA Configuration Loading Using Validation and Stop Bits
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Solution Overview
Problem
Existing programmable logic devices (PLDs) face issues with inadvertently loading invalid or corrupted configuration data due to power failures during the loading process, leading to improper operation or damage, and lack control over loading configuration data when powered up.
Innovation Solution
Incorporating a non-volatile memory with a validation bit and a stop bit, along with control logic that determines whether to transfer configuration data based on the logic states of these bits, allowing selective loading and preventing inadvertent data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single validation bit is used to indicate successful loading of configuration data, then the loading process is simple and fast, but power failures during pre-programming can cause the validation bit to be erroneously set, leading to invalid configuration data being loaded
Solution Approach 1:
The single validation bit is segmented into multiple validation bits (first validation bit and second validation bit). These bits work together to provide more reliable validation through their combined logic states, reducing the probability of erroneous validation while maintaining a relatively simple structure.
Solution Approach 2:
The patent performs preliminary validation by checking the logic states of multiple validation bits before allowing configuration data to be loaded from non-volatile memory to configuration memory. This preliminary check prevents invalid data from being loaded, addressing the reliability issue before the actual loading occurs.
2Ease of operation
If a single validation bit automatically triggers configuration data loading when powered up, then the loading process is automatic and convenient, but users cannot control or prevent loading when desired for particular applications
Solution Approach 1:
The system dynamically adjusts the loading behavior based on the states of multiple validation bits. Different combinations of validation bit states can trigger different loading behaviors, allowing the system to be both automatic (when validation succeeds) and controllable (when validation fails or specific patterns are detected), thus providing adaptability while maintaining ease of operation.
3Device complexity
If configuration data is loaded from non-volatile memory to configuration memory without additional validation bits, then the device structure is simple, but invalid or corrupted data may be loaded causing improper operation or damage
Solution Approach 1:
Multiple validation bits act as intermediaries between the non-volatile memory and the configuration memory. These bits do not store configuration data themselves but mediate the loading process by providing validation information that determines whether data should be transferred, thus protecting against invalid data loading while adding minimal complexity.
Data Source
AI summary
In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.