FPGA Verification Module for SoC Signal Observability
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Solution Overview
Problem
Highly-integrated system-on-chip (SoC) devices face challenges in design verification due to limited visibility and control over signal values, particularly in FPGA-based verification systems, which struggle to isolate root cause errors due to restricted access and limited sample capture depth.
Innovation Solution
A prototype system comprising a first interface component for sending a configured image of a user design and a verification module, along with a second interface component for providing timing and control information, allows for improved observability and control of device states through instrumentation circuitry and logic modules that can sample signal values, perform state analysis, and trigger events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FPGA-based verification systems are used to improve system execution time, then speed is improved, but observability and control of signal values deteriorate
Solution Approach 1:
The patent introduces an intermediary verification module that sits between the FPGA prototype system and the design under verification. This module captures and stores signal values from multiple interfaces (I/F1, I/F2, I/F3) in memory, allowing comprehensive observation of signal states without slowing down the FPGA execution. The intermediary acts as a buffer that preserves full signal visibility while maintaining system speed.
2Productivity
If FPGA vendor-specific verification tools are used, then verification capabilities are provided, but access to limited number of signals and limited sample capture depth restrict error isolation
Solution Approach 1:
The patent segments the verification system into multiple independent interface components (I/F1, I/F2, I/F3) that can be configured to access different parts of the design. Each interface can independently capture signals with extended depth, and the verification module combines data from all segments. This segmentation allows unlimited total sample capture depth by distributing the capture across multiple interfaces rather than being limited by a single tool's capabilities.
3Measurement precision
If comprehensive signal monitoring is implemented to improve error isolation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The verification module is designed as a universal, multi-functional component that can monitor all signal types (data, control, clock) from multiple interfaces through a single unified architecture. Rather than implementing separate monitoring systems for each interface, the single verification module handles all observation and control functions, reducing overall system complexity while maintaining comprehensive measurement precision.
Data Source
AI summary
Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.