FPGA Virtual Logic Tile Arrays for Independent Multi-Function Partitioning
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Solution Overview
Problem
Current FPGA technologies lack the ability to efficiently partition and configure physical arrays of logic tiles into virtual arrays that can operate independently or dependently, with distinct clock domains and I/O configurations, limiting their flexibility and functionality in implementing diverse functions and operations.
Innovation Solution
The integration of a field programmable gate array (FPGA) with a physical array of logic tiles that can be functionally partitioned into virtual arrays, allowing for independent or dependent operation, with customizable clock signals and I/O configurations, enabling the implementation of various functions such as data processors, accelerators, and encryption engines through a compiler-generated composite bitstream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the physical array of logic tiles is partitioned into multiple virtual arrays with independent configurations, then the adaptability and functionality of the FPGA is improved, but the device complexity increases due to multiple configuration management requirements
Solution Approach 1:
The physical array of logic tiles is segmented into multiple virtual arrays, where each virtual array can be independently configured and managed. This segmentation allows different portions of the FPGA to perform different functions simultaneously, improving adaptability while the segmentation itself manages the complexity by creating manageable independent units.
Solution Approach 2:
The same physical logic tile array can be universally configured to perform multiple different functions through the creation of different virtual arrays. Each virtual array can be programmed with different bitstreams to implement various logic functions, making the FPGA multi-functional without requiring additional physical hardware.
2Adaptability or versatility
If virtual arrays are configured to operate independently with separate clock domains, then the operational flexibility is improved, but the programming complexity increases
Solution Approach 1:
The clocking system is segmented into multiple independent clock domains, with each virtual array able to operate with its own clock signal. This allows independent timing control for different functional blocks while the segmentation manages the complexity by creating separate, manageable clocking subsystems.
Solution Approach 2:
The FPGA configuration is made dynamic, allowing virtual arrays to be created, modified, and deleted at runtime. Clock domains can be dynamically assigned to virtual arrays as they are created, and the system can adapt its operational structure in real-time without requiring complete reconfiguration.
3Adaptability or versatility
If the FPGA supports multiple virtual arrays with different I/O configurations, then the versatility is improved, but the ease of operation decreases due to complex configuration management
Solution Approach 1:
I/O resources are segmented and assigned to specific virtual arrays, allowing each virtual array to have its own dedicated I/O configuration. This segmentation simplifies management by associating I/O resources with their parent virtual array, making it easier to track and configure despite the overall system complexity.
Solution Approach 2:
The system provides self-service through automated configuration management, where the FPGA infrastructure automatically handles the complex tasks of allocating I/O resources to virtual arrays, managing clock domains, and coordinating inter-array communications, reducing the manual configuration burden on users.
4Productivity
If logic tiles are partitioned into virtual arrays for specific functions, then the productivity for implementing diverse functions is improved, but the device complexity increases due to inter-array communication requirements
Solution Approach 1:
An interconnect fabric acts as an intermediary between virtual arrays, providing standardized communication pathways and protocols. This mediator simplifies the complexity of inter-array communication by offering a uniform interface that abstracts the underlying physical connections and timing requirements.
Solution Approach 2:
The interconnect fabric provides universal communication capabilities that can be used by any virtual array to communicate with any other virtual array or external devices. This multi-functional communication infrastructure supports various data transfer modes and protocols, reducing the need for specialized communication paths for each virtual array pair.
Data Source
AI summary
An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.