Intra-regulator Current Balancing in FPGA Voltage Regulators
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Solution Overview
Problem
Custom-designed power management integrated circuits (PMICs) for system on a chip (SoC) are inefficient and often have unbalanced voltage regulators, compromising performance, as they need to be tailored for each type of SoC, and current balancing mechanisms between voltage regulators are not effectively implemented.
Innovation Solution
A generic PMIC with a field programmable array of voltage regulators that can adaptively support various SoCs by using intra-regulator and inter-regulator current balancing mechanisms, allowing each voltage regulator to balance its current paths and output currents independently, and enabling redundancy through a bypass unit to decouple voltage regulators from power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom-designed PMICs are used for each SoC type, then performance can be optimized for specific applications, but manufacturing efficiency decreases and design complexity increases
Solution Approach 1:
The patent implements a field programmable array of voltage regulators that can be configured to support multiple SoC types through programmable control logic. The PMIC contains an array of identical voltage regulator units that can be programmed via I2C interface to provide different voltage rail configurations, eliminating the need for custom-designed PMICs for each SoC type while maintaining manufacturing efficiency
2Power
If voltage regulators are densely packed in PMIC, then power distribution capability increases, but current balancing between regulators becomes difficult and performance is compromised
Solution Approach 1:
The patent implements inter-regulator current balancing mechanisms where each voltage regulator unit includes feedback circuitry that monitors its output current and adjusts its operation based on the currents of adjacent regulators. This feedback system ensures equal current distribution across all active regulators in the array, preventing current imbalance even when regulators are densely packed
Solution Approach 2:
The patent introduces intermediary balancing circuits that act as mediators between adjacent voltage regulator units. These intermediary circuits measure current differences between regulators and provide correction signals to equalize current distribution, enabling dense packing without sacrificing current balancing performance
3Device complexity
If fixed configuration PMICs are used, then design simplicity is maintained, but adaptability to different SoC types is reduced
Solution Approach 1:
The patent transforms the static, fixed configuration of traditional PMICs into a dynamic, reconfigurable system. The voltage regulator array can be programmatically configured through I2C interface to adapt to different SoC power requirements, enabling a single PMIC design to serve multiple SoC types while maintaining operational simplicity through standardized control protocols
Data Source
AI summary
A semiconductor device has a power rail that provides a rail voltage. The power rail is electrically coupled to a plurality of voltage regulators, and each voltage regulator includes an output interface electrically coupled to the power rail, and a first drive path and a second drive path both coupled to the output interface, and an intra-regulator balancing circuit. The first and second drive paths are coupled in parallel with each other, and operate during a first phase and a second phase, at an operating frequency, to provide a first path current and a second path current to the power rail, respectively. The intra-regulator balancing circuit senses the first and second path currents and controls a first duty cycle of the first phase and/or a second duty cycle of the second phase based on a difference of the first and second path currents.