FPGA Configuration Watermarking for Version Identification
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Solution Overview
Problem
Existing FPGA devices face challenges in distinguishing between devices based on similar intellectual property designs, leading to difficulties in verifying the configuration version of a particular device.
Innovation Solution
A computer-implemented method is introduced that defines a device capable of implementing logic functions by utilizing a memory bus with an address space, program memory cells, and auxiliary memory cells. The method involves obtaining a checksum value, finding a digital value that satisfies a predefined rule when applied to the checksum value, and defining an augmented digital definition that includes the digital definition of logic functions and auxiliary memory cells reflecting the checksum value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are configured with programmable logic blocks and routing areas to implement various functions, then the device becomes highly flexible and reprogrammable, but it becomes difficult to determine unambiguously which configuration version a particular device implements
Solution Approach 1:
The patent embeds a version identification code into the FPGA device during the configuration process, before the device is deployed. This preliminary action ensures that the version information is already present in the device, eliminating the need for external verification and allowing unambiguous identification of the configuration version at any later time.
Solution Approach 2:
The patent introduces an intermediary version identification code that acts as a mediator between the reconfigurable logic blocks and the external verification system. This code is stored in a dedicated memory location and can be read to determine the configuration version, without interfering with the normal reprogrammable operation of the FPGA.
2Ease of manufacture
If multiple iterations of a given design are based on similar intellectual property, then the device can be easily manufactured and configured, but it becomes difficult to distinguish one device from another
Solution Approach 1:
The patent applies local quality by embedding unique version identification codes at specific locations within the FPGA device structure. While the overall design may be reused across multiple devices, the local version identification code provides distinctive information that allows precise differentiation between device iterations, maintaining both manufacturing efficiency and device distinguishability.
3Adaptability or versatility
If the device configuration can be changed at different times and levels, then the device becomes more adaptable, but it becomes more complex to verify the configuration version
Solution Approach 1:
The patent extracts the version identification information from the complex configuration data and places it in a separate, dedicated memory location. This extraction simplifies the verification process, as the version code can be read independently without needing to analyze the entire configuration set, thereby reducing verification complexity while maintaining configuration flexibility.
Data Source
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AI summary
A method of defining a logic device is provided in which the definition incorporates the definition of special auxiliary memory cells reserved for the presentation of a special code, incorporating a signature of the definition as a whole so as to constitute a watermark securing the design as a whole, and possibly other information. In certain embodiments, the special code may incorporate recursive signatures from preceding versions of the same device to as to constitute a watermark blockchain. A LUT based FPGA architecture is proposed with special addressable memory cells reserved for this purpose, in which case a programming bitstream may constitute a definition in accordance with the inventive method.