FPGA Waveform Capture Macro for High-Speed Signal Verification
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Solution Overview
Problem
Conventional FPGA-based hardware emulation for integrated circuits faces limitations due to restrictive physical probes, slow serial scan-chain mechanisms, and inefficient signal capture and memory management, leading to hardware resource constraints, inefficiencies, and performance degradation.
Innovation Solution
The QiWC waveform-capture macro allows for dynamic signal selection at runtime, utilizing a pre-compiled, self-contained block that minimizes hardware resources and separates the design from the capture mechanism, enabling efficient waveform dumping and high-speed data transfer without requiring additional synthesis or place-and-route operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated hardware is used for each captured signal to enable high-speed concurrent capture, then capture speed is improved, but hardware resource consumption increases significantly
Solution Approach 1:
The system divides the capture functionality into multiple hierarchical levels: top-level capture signals, intermediate macro-level capture signals, and bottom-level individual signal capture. This segmentation allows concurrent capture of multiple signals at different hierarchy levels simultaneously, improving overall capture speed while distributing hardware resource usage across multiple manageable units rather than requiring dedicated hardware for every single signal.
Solution Approach 2:
The macro structure serves multiple functions: it captures signals concurrently at its level, buffers the captured data, and manages transfer to host memory. This multi-functionality eliminates the need for separate dedicated hardware for each signal's capture, buffering, and transfer operations, thereby reducing overall hardware resource consumption while maintaining high capture speed.
2Quantity of substance
If the number of signals to be captured is increased, then measurement capability is improved, but hardware resources are depleted and capacity is reduced
Solution Approach 1:
The system hierarchically segments signals into top-level and macro-level capture groups. This allows a large total number of signals to be captured by distributing them across multiple macro instances, each handling a subset of signals. The hierarchical structure enables scaling to capture many more signals than would be possible with a flat structure, as each macro operates semi-independently with its own buffering resources.
Solution Approach 2:
The system adds a hierarchical dimension to signal capture organization. Instead of capturing all signals at a single level, it creates multiple hierarchy levels (top-level macros containing nested macro-level signals). This dimensional change allows exponential scaling of capture capacity, as signals can be organized in tree structures where N top-level macros can each contain M nested macros, capturing N×M signals with manageable hardware resources at each level.
3Quantity of substance
If memory size is increased to store more waveform data, then data storage capacity is improved, but data transfer time to host increases due to sharing limited communication resources
Solution Approach 1:
The system segments the large waveform data storage into multiple smaller buffers distributed across different macro instances. Each macro has its own dedicated buffer and can transfer data to host memory independently. This segmentation allows parallel data transfer operations, where multiple macros simultaneously transfer their captured data, thereby reducing total transfer time even as overall storage capacity increases.
Solution Approach 2:
The system implements continuous capture and transfer operations by allowing multiple macros to operate concurrently. While one macro is transferring its buffered data to host memory, other macros continue capturing and buffering signals. This overlapping of capture and transfer operations across multiple hierarchical levels ensures continuous useful action, maximizing data throughput and minimizing idle time in the data transfer pipeline.
4Adaptability or versatility
If signal capture configuration is changed after compilation, then adaptability is improved, but compilation and place-and-route processes must be reexecuted causing delays
Solution Approach 1:
The system performs preliminary configuration of the macro structure and capture hierarchy during the initial compilation, establishing the framework for signal capture. However, the specific signal selections and groupings can be modified at runtime without full recompilation. This preliminary setup allows the system to maintain adaptability for signal selection changes while avoiding the time-consuming full place-and-route process, as only localized adjustments are needed rather than complete reconfiguration.
Data Source
AI summary
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.