FPGA Convolution Acceleration via Winograd Algorithm and Three-Buffer Architecture
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Solution Overview
Problem
Current CNN acceleration methods face challenges in efficiently processing convolution operations due to high computing complexity and resource constraints, particularly in embedded platforms like FPGAs and ASICs, where memory and bandwidth limitations hinder optimal performance.
Innovation Solution
The proposed solution involves a convolution acceleration method that utilizes an FPGA-based architecture with a three-buffer system for on-chip memory, employing a FIFO port for data transfer and matrix dot product operations, and applying the Winograd algorithm to reduce the number of multiplications, thereby optimizing resource utilization and improving computing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional CNN convolution operations are performed directly on FPGAs, then computing accuracy is improved, but computing complexity and resource consumption increase significantly
Solution Approach 1:
The patent transforms the convolution computation parameters by converting traditional point-to-point convolution into surface-to-surface convolution using Winograd algorithm. This changes the computational paradigm from multiplying individual pixel values to performing matrix operations on transformed input windows, reducing the number of multiplications required while maintaining computational accuracy.
Solution Approach 2:
The patent replaces the traditional mechanical convolution process with an optimized computational system based on Winograd algorithm. Instead of directly applying filter kernels to input images through repeated multiplications, the system uses pre-computed constant matrices to transform inputs and kernels, performs a single matrix multiplication, then transforms the result, substituting the traditional iterative mechanical process with a more efficient mathematical transformation approach.
2Speed
If more memory resources are allocated for on-chip buffering, then data processing speed is improved, but device area and cost increase
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing constant matrices (G, B, A) in the FPGA's on-chip memory before processing begins. These pre-computed transformation matrices are loaded once and reused throughout the convolution process, eliminating the need to perform repeated matrix computations and reducing the amount of data that needs to be buffered during processing.
Solution Approach 2:
The patent segments the convolution process into distinct phases (input transformation, kernel transformation, matrix multiplication, output transformation) with dedicated buffering for each phase. The on-chip memory is divided into multiple buffers that handle different stages of computation, allowing efficient data reuse and minimizing the total memory requirement compared to buffering entire images or feature maps.
3Productivity
If FPGA reconfigurability and parallel computing are utilized for convolution acceleration, then computing efficiency is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent implements continuous useful action by organizing the convolution computation as a pipelined process where input data flows continuously through the FPGA fabric. The Winograd algorithm's matrix transformation structure allows for continuous streaming computation where each clock cycle processes a new set of input values, keeping the computational resources continuously utilized without idle cycles between operations.
Solution Approach 2:
The patent employs dynamic resource allocation in the FPGA implementation, where the computational architecture adapts to different convolution configurations. The FPGA's reconfigurable logic dynamically adjusts the number and size of parallel computation units based on the specific convolution parameters (kernel size, input channels, output channels), optimizing the balance between computing efficiency and power consumption for each specific task.
Data Source
AI summary
A convolution acceleration and computing processing method includes: reading data to be processed of a preset size in a task to be processed from an off-chip memory of an accelerator sequentially through a FIFO port, and storing the data to be processed into at least one input buffer of a first buffer in an on-chip memory of the accelerator; responsive to data to be processed being stored into an input buffer, reading input window data to be processed from the at least one input buffer sequentially, performing convolution on the input window data to be processed by using the convolution kernel data to obtain output window data and storing the output window data in the third buffer; and storing the output window data in the third buffer into the off-chip memory sequentially through the FIFO port.