FPGA Wiring Topology Detection Using Pin-Level Self-Test
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Solution Overview
Problem
Existing methods for verifying the correct wiring between FPGAs are complex and prone to errors, which can lead to communication failures or damage to the FPGAs.
Innovation Solution
A method that uses interface pins with drivers and registers to automatically detect and verify connections by transmitting signals and checking for their receipt, eliminating the need for manual verification and allowing for the detection of hidden faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If manual testing methods are used to verify wiring connections between FPGAs, then the verification process can be performed with simple equipment, but the verification time becomes very long and the process becomes complex
Solution Approach 1:
The verification system performs self-testing by automatically generating test signals from transmit registers, routing them through the wiring connections, and capturing responses in receive registers. The FPGA architecture itself serves as the test equipment, eliminating the need for external manual testing tools and significantly reducing verification time.
Solution Approach 2:
Test patterns are pre-loaded into transmit registers before the verification process begins. This preliminary preparation allows the actual connection verification to proceed rapidly without requiring real-time signal generation, thereby reducing the overall verification time while maintaining systematic testing coverage.
2Reliability
If comprehensive wiring verification is performed to detect all potential faults, then the reliability of FPGA connections is improved, but the complexity of the detection process increases
Solution Approach 1:
The verification process is segmented into independent transaction units, each consisting of a transmit register, a receive register, and associated control logic. This segmentation allows comprehensive verification of multiple connections to be performed through a series of simple, repeatable transactions, reducing the overall detection complexity while maintaining high reliability.
Solution Approach 2:
The system implements feedback by comparing the test signals transmitted through connections with the signals captured in receive registers. This feedback mechanism automatically identifies faults without requiring complex external analysis equipment, thereby improving connection reliability detection while keeping the verification process manageable.
3Loss of information
If unique identification data is loaded into driver registers to identify connections, then the connection mapping can be determined, but the verification process becomes time-consuming
Solution Approach 1:
Instead of using complex unique identification data sequences, the system changes the parameter being tested to simple binary test patterns (0s and 1s). This parameter simplification maintains connection identification accuracy while dramatically reducing the time required for verification, as simple patterns can be generated and recognized much faster than complex identification sequences.
4Manufacturing precision
If multiple transactions are used to verify different pin connections, then complete wiring topology detection is achieved, but the overall verification time increases
Solution Approach 1:
The verification process uses periodic transactions where each transmit register systematically cycles through its connection partners. By organizing the verification as periodic, structured transactions with consistent patterns and timing, the system achieves complete wiring topology detection while minimizing total verification time through efficient resource utilization and parallel processing capabilities.
Data Source
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AI summary
Method for detecting a wiring topology between two FPGAs. A first FPGA comprises a plurality of interface pins, in particular a first interface pin. A second FPGA comprises a plurality of interface pins, in particular a second interface pin. A plurality of lines connects some of the interface pins of the first FPGA to some of the interface pins of the second FPGA. A first driver is present at the first interface pin. A first receive register is implemented at the second interface pin. A first transmit register is implemented at the first driver. The transmit register defines the signal output by the first driver. The first driver is activated by a first activation signal. The first driver transmits a first signal. The first receive register is used to determine whether the first signal is received at the second interface pin.The second interface pin is assigned to the first interface pin when the signal from the first driver is received at the second interface pin.