FPGA Logic and X/Y Routing for Lower Delay Variability
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Solution Overview
Problem
Existing Field Programmable Gate Arrays (FPGAs) face challenges with exponentially increasing circuit expenditure for combinatorial boolean functions and unfavorable routing delays, particularly in clock lines, due to the use of Look Up Tables (LUTs) and Manhattan routing structures.
Innovation Solution
The implementation of configurable logic elements that can be adjusted between different boolean operations, utilizing symmetric functions like AND, OR, NAND, NOR, XOR, and XNOR, which allows for linearly increasing operational expenditure and a X/Y routing structure to minimize signal delay, enabling efficient realization of combinatorial logic and reducing clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Look Up Tables (LUTs) are used to realize combinatorial boolean functions, then any arbitrary boolean function can be implemented, but the circuit expenditure increases exponentially with the number of inputs
Solution Approach 1:
The patent segments the boolean function implementation into multiple stages using configurable logic elements (CLEs) with a limited number of inputs (e.g., 4-input CLEs). Instead of using a single large LUT that would exponentially grow in complexity, the system divides the function into smaller sub-functions implemented across multiple CLEs, reducing the circuit expenditure at each stage while maintaining the ability to implement arbitrary boolean functions through composition.
Solution Approach 2:
The patent transitions from a two-dimensional LUT structure to a multi-dimensional architecture using multiple layers of configurable logic elements interconnected through routing resources. This dimensional expansion allows the system to implement complex boolean functions by distributing logic across spatial dimensions (multiple CLE layers and routing channels) rather than concentrating all logic in a single exponentially-growing LUT.
2Ease of manufacture
If Manhattan routing structure is used for interconnections, then routing is simplified and easier to implement, but the signal delay becomes highly dependent on the number of serially linked sections causing significant delay fluctuation and clock skew
Solution Approach 1:
The patent introduces dynamic routing capabilities where the routing structure can adaptively select different paths based on destination and timing requirements. Instead of fixed Manhattan routing, the system provides multiple routing options (short paths, long paths, clock paths) that can be dynamically configured to optimize signal delay characteristics for different connections, reducing delay variability and clock skew.
Solution Approach 2:
The patent changes the routing parameters by providing multiple path length options and routing styles (Manhattan, direct, clock routing) for different signal types. This allows the system to adjust routing parameters (path length, routing layer selection) to minimize delay variability for critical signals while maintaining the structured approach of Manhattan routing for non-critical connections.
Data Source
AI summary
Some Gate Arrays and in particular Filed Programmable Gate Arrays (FPGAs), realize combinatorial logic by utilizing so-called “Look Up Tables” (LUTs). Unfortunaltely the circuit expenditure for a LUT is exponentially increasing with the number of inputs. The invention overcomes this problem by using a set of gates as AND, NAND, OR, NOR, XOR, XNOR, AND/OR combination gate, AND/NOR combination gate, OR/AND combination gate, OR/NAND combination gate, identity comparator between two vectors, multiplexer and adder.In addition, conventional GAs and FPGAs utilize routing structures and channels that allow a so-called Manhattan routing. This has the disadvantage that the signal delay on such a connection is highly dependent on the number of serially linked sections. Consequently, the delay time fluctuates significantly on different connections. The invention overcomes this problem by using a X/Y routing structure with a fixed number of connection points and a fixed local routing.