FPMOS Termination Structure for Higher Avalanche Resistance
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Solution Overview
Problem
The termination region of an FPMOS (field plate metal-oxide-semiconductor) has low avalanche resistance, making it susceptible to destruction due to potential rises and parasitic bipolar transistor operation.
Innovation Solution
The semiconductor device incorporates a design with a specific arrangement of semiconductor layers and electrodes, including a high concentration of second conductivity type impurities in the termination region, combined with insulation films and a field plate structure, to enhance avalanche resistance without increasing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the termination region is designed with conventional structure, then the device complexity is low, but the avalanche resistance is low making it susceptible to destruction
Solution Approach 1:
The patent applies local quality by creating a guard ring structure with specific doping characteristics only in the termination region, while keeping the cell region structure conventional. The guard ring has a doping concentration and depth specifically optimized for the termination region to provide localized avalanche protection without affecting the overall device complexity significantly.
Solution Approach 2:
The termination region is segmented into multiple zones including the guard ring structure with different doping concentrations and depths. This segmentation allows each zone to perform specific functions - the guard ring provides avalanche protection while other regions maintain their conventional structures, thus improving reliability without proportionally increasing complexity.
2Reliability
If impurity concentration is increased to improve avalanche resistance, then the avalanche resistance improves, but the on-resistance increases
Solution Approach 1:
The patent implements local quality by concentrating high impurity concentration specifically in the guard ring structure of the termination region, while maintaining lower impurity concentrations in the cell region. This localized approach ensures that avalanche resistance is improved where needed (termination region) without increasing on-resistance in the current-carrying cell region.
Solution Approach 2:
The impurity distribution is segmented into different concentration zones - high concentration in the guard ring for avalanche protection and low concentration in the cell region for maintaining low on-resistance. This segmentation allows independent optimization of avalanche resistance and on-resistance in different regions of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively improves the avalanche resistance in the termination region while preventing the operation of parasitic bipolar transistors, thereby enhancing the device's reliability and performance.
Implementation Method 1
The distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in the second region surrounding the first region is smaller than the distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in the first region
Data Source
AI summary
A semiconductor device according to the present embodiment includes a semiconductor area, a first electrode, a second electrode, a control electrode, and a third electrode. The semiconductor area includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The semiconductor area further includes a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. A distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in a second region surrounding the first region is smaller than a distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in the first region.