Fraction-N Frequency Divider With Glitch-Free Phase Switching
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Solution Overview
Problem
Existing frequency dividers are primarily designed for integer frequency dividing, making it difficult to perform fractional frequency dividing operations effectively, which restricts their practical application in systems requiring such processing.
Innovation Solution
A fraction-N frequency divider circuit comprising a multi-phase clock generator, phase selectors, a glitch-free multiplexer, and a control circuit that generates and switches clock signals to produce a glitch-free frequency-divided signal, enabling fractional frequency dividing operations by alternately adjusting phase selecting signals to prevent glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an integer frequency divider is used, then the circuit structure is simple, but it cannot perform fractional frequency dividing operations
Solution Approach 1:
The frequency divider is divided into multiple integer frequency dividers (first, second, third, fourth) that operate in sequence during different time periods. Each divider handles a specific portion of the division ratio, allowing the system to achieve fractional division through time-multiplexed integer divisions rather than requiring a single complex fractional divider circuit.
Solution Approach 2:
The patent employs dynamic switching between different integer frequency dividers using phase selectors and multiplexers. The system dynamically changes which divider is active based on the current time period, enabling the same hardware to perform different division ratios sequentially. This dynamic operation allows fractional frequency division to be achieved through time-varying integer divisions.
2Adaptability or versatility
If clock signals are switched between different phases, then fractional frequency division is enabled, but glitches may occur during switching
Solution Approach 1:
The phase selectors are designed to pre-align the phases of clock signals before switching occurs. By ensuring that the outgoing and incoming clock signals are properly phased relative to each other before the actual switching event, the system prevents phase mismatches and potential glitches that would otherwise occur during dynamic phase transitions.
Solution Approach 2:
The patent introduces phase selectors as intermediary components between the clock signal sources and the frequency dividers. These selectors act as mediators that carefully manage the phase relationships and timing of clock signals during transitions, ensuring smooth handover between different phases without causing signal instability or glitches in the final output.
3Adaptability or versatility
If multiple integer frequency dividers are used for fractional division, then fractional frequency dividing is achieved, but the control circuit becomes more complex
Solution Approach 1:
The control circuit operates periodically, cycling through different integer frequency dividers in a predetermined sequence. Each divider is activated for a specific time period corresponding to its assigned division ratio portion. This periodic switching pattern simplifies control logic compared to arbitrary switching, as the circuit only needs to manage regular, repeating cycles rather than complex adaptive control for each transition.
Data Source
AI summary
A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.