Fractional Bit Encoding for Non-Power-of-Two Modulation Formats

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Solution Overview

Problem

Conventional encoding methods are inefficient when dealing with modulation formats where the number of available code words is not a power of two, as they can only utilize an integer number of bits per symbol, leaving unused code words and reducing transmission capacity.

Innovation Solution

A fractional bit encoder and decoder system that re-multiplexes bit streams to determine the class of bit combinations, allowing for either n or n+1 bits to be encoded per symbol, maximizing the use of available code words and increasing transmission capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional encoding methods are used with modulation formats where the number of code words is not a power of two, then the encoding process is simple and straightforward, but the transmission capacity is reduced due to unused code words

Engineering Contradiction:
Improvetransmission capacityVSAvoidencoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention segments the code words into two distinct classes: first class code words that are encoded using n bits, and second class code words that are encoded using n+1 bits. This segmentation allows the system to fully utilize all M code words rather than leaving unused code words, thereby increasing transmission capacity while managing encoding complexity through structured classification

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces dynamic encoding where the number of bits per symbol varies depending on the class of code word. The encoder dynamically selects between encoding n bits or n+1 bits based on which class the current code word belongs to, allowing the system to adapt and maximize information transmission efficiency rather than being constrained to a fixed integer number of bits per symbol

Inventive Principle:
Principle #15Dynamics

2Loss of information

If an integer number of bits per symbol is used, then the encoding process is straightforward, but the information capacity is not fully utilized

Engineering Contradiction:
Improveinformation capacity utilizationVSAvoidencoding operation simplicity
Core Design Contradiction:
Loss of informationVSEase of operation

Solution Approach 1:

The invention changes the parameter of bits per symbol from a fixed integer value to a variable value that can be either n or n+1 bits depending on the code word class. This parameter change allows the system to achieve fractional bits per symbol on average, fully utilizing the information capacity of the modulation format while maintaining relatively simple encoding operations through predefined class assignments

Inventive Principle:
Principle #35Parameter changes

3Productivity

If all M code words are fully utilized, then transmission capacity is maximized, but the encoding complexity increases due to non-integer bits per symbol

Engineering Contradiction:
Improvetransmission capacityVSAvoidencoder complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention applies preliminary action by pre-classifying all M code words into first class and second class groups before the encoding process. This pre-classification establishes clear rules for which code words receive n bits and which receive n+1 bits, allowing the encoder to operate with simple lookup-based logic rather than complex calculations, thus maximizing transmission capacity while keeping encoder complexity manageable

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2413530B1An apparatus and a method for performing a fractional bit encoding and decoding
Publication Date: 2016.06.29 ADVA OPTICAL NETWORKING SP ZOO
  • EP2413530B1 patent drawingFigure 1
  • EP2413530B1 patent drawingFigure 2
  • EP2413530B1 patent drawingFigure 3

AI summary

The invention relates to a fractional bit encoder (1) and a method for encoding a data stream into code word identifiers for a physical line encoder (13), wherein said fractional bit encoder (1) comprises a (1:K) demultiplexer (3) for a de-multiplexing a received data stream into a predetermined number (K) of bit streams, a first (K1:n) multiplexer (4) for re-multiplexing a first number (K1) of said K bit streams onto n parallel lines transporting n re-multiplexed bit streams and a second multiplexer (5) re-multiplexing a second number (K2) of said K bit streams (K2:1)onto a single line transporting one further re-multiplexed bit stream, wherein n = [ld(M)] and M being a configurable number of different code word identifiers, a class detector (7) which evaluates the first n re-multiplexed bit streams to determine a class of the respective bit combination and a word encoder (10) which encodes the respective bit combination depending on the determined class of the bit combination.