Fractional Bit Programming in Stacked Memory Arrays

The patent divides the memory array into multiple separate memory arrays (first memory array, second memory array, third memory array, etc.), each containing a population of memory cells. By distributing memory cells across multiple arrays with separate peripheral circuitry and data bus taps, the system can perform parallel operations on different cell populations, thereby maintaining high programming speeds even while using multi-level cell structures for increased storage capacity.

The patent introduces a vertical stacking dimension by positioning memory arrays at different spatial locations (first memory array at a first location, second memory array at a second location, etc.) and connecting them via data bus taps. This three-dimensional arrangement allows parallel processing of multiple cell populations simultaneously, resolving the speed-density tradeoff by adding a spatial dimension to the architecture.

The patent segments the memory system into multiple independent memory arrays, each with its own peripheral circuitry and data bus tap connections. This segmentation allows the system to manage stress and errors at the array level rather than the individual cell level, improving overall durability by isolating failures and reducing the cumulative impact of programming errors across the entire memory structure.

The patent applies different operational characteristics to different memory arrays by providing separate peripheral circuitry and independent data bus tap connections for each array. This allows localized optimization where each array can be managed independently, with its own read/write circuits and sense amplifiers, thereby maintaining higher reliability margins even as storage density increases through multi-level cell structures.

The patent divides the three-dimensional memory structure into multiple separate memory arrays positioned at different spatial locations. Each array has its own charge trapping regions that are physically separated and independently managed. This segmentation maintains adequate separation between charge trapping regions across the entire structure, preventing interference and retention issues that would occur in a densely packed monolithic three-dimensional array.

The patent utilizes multi-dimensional spatial arrangement by positioning memory arrays at different locations (first location, second location, third location, etc.) and connecting them through vertical or lateral data bus taps. This approach distributes charge trapping regions across multiple spatial dimensions, ensuring sufficient physical separation is maintained even as overall storage capacity increases, thereby preserving data retention reliability.

The patent divides the memory system into multiple arrays that can be accessed in parallel. Each array can use a reduced number of read levels (such as single-level or dual-level reading) while the overall system achieves high storage capacity through the combination of multiple arrays. This segmentation allows simpler, faster read operations at the array level while maintaining high system-level storage density.

The patent achieves high storage capacity by adding a spatial dimension with multiple memory arrays positioned at different locations and connected via data bus taps, rather than increasing the number of read levels within a single array. This dimensional approach allows each array to operate with fewer read levels and faster read speeds, while the aggregate storage capacity across all arrays remains high.