Fractional Bits Per Cell Flash Storage Low-Latency Read
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Solution Overview
Problem
Conventional NAND flash memory systems require a high number of reads to determine the program state of each cell, leading to increased latency as the number of programmable states increases, especially when storing fractional bits per cell.
Innovation Solution
Implementing a multi-page construction method where each NAND flash memory cell is programmed to a fractional number of bits, allowing for reduced read operations by applying fewer read voltages than the total number of program states, thereby distributing data across multiple pages to minimize reads per page.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of program states per cell is increased to store more bits per cell, then storage density is improved, but the number of reads required to determine the program state increases, leading to increased latency
Solution Approach 1:
The patent divides the data storage into multiple pages (first page, second page, third page) where each page stores a portion of the total data bits. By segmenting the data across multiple pages, the system can retrieve different portions of data with fewer reads per page, thereby reducing overall read latency while maintaining high storage density through multi-level cells.
2Ease of operation
If conventional single-page construction is used, then data retrieval is straightforward, but the number of reads per page is high, increasing latency
Solution Approach 1:
The patent transitions from a single-page construction to a multi-page construction, adding a dimensional aspect to data organization. By distributing data across multiple pages with different read voltage requirements, the system reduces the number of reads needed per page while maintaining ease of operation through structured data distribution.
3Measurement precision
If L-1 read voltages are applied to determine program state, then measurement precision is improved, but the number of read operations increases, worsening productivity
Solution Approach 1:
The patent applies partial read actions by using fewer read voltages per page (M, N, O reads) compared to the full L-1 reads required for complete program state determination. This partial action approach achieves sufficient measurement precision for each page's data portion while significantly improving overall data retrieval productivity.
Data Source
AI summary
Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.