Fractional Clock Generator Using Analog Interpolation for Low Jitter
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Solution Overview
Problem
Modern electronic systems require diverse clock frequencies with different noise/jitter tolerances, which are difficult to generate using a single universal clock oscillator, often necessitating multiple phase-locked loops (PLLs) that lead to power consumption issues and frequency accuracy problems due to cross-talk.
Innovation Solution
A full quadrant analog interpolator is used in a fractional clock generator to eliminate the need for multiple PLLs, utilizing a quadrature clock signal with minimal jitter, and a multi-stage comparator to minimize delay dispersion, allowing digital control of the delay and providing a differential output to an integer divider for the final output clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are used to generate diverse clock frequencies, then frequency diversity is improved, but power consumption increases and frequency accuracy deteriorates due to cross-talk
Solution Approach 1:
The patent merges multiple PLL functions into a single PLL by adding a fractional divider stage. Instead of using separate PLLs for different clock domains, one PLL generates a high-frequency output that is then divided by fractional values to produce multiple lower frequencies. This combining approach reduces the total number of PLL circuits, thereby reducing power consumption and eliminating cross-talk between multiple PLLs while maintaining the ability to generate diverse frequencies through the fractional division mechanism.
2Adaptability or versatility
If multiple PLLs are used to generate diverse clock frequencies, then frequency diversity is improved, but frequency accuracy deteriorates due to cross-talk between PLLs
Solution Approach 1:
The patent merges multiple PLL functions into a single PLL by adding a fractional divider stage. Instead of using separate PLLs for different clock domains, one PLL generates a high-frequency output that is then divided by fractional values to produce multiple lower frequencies. This combining approach reduces the total number of PLL circuits, thereby reducing power consumption and eliminating cross-talk between multiple PLLs while maintaining the ability to generate diverse frequencies through the fractional division mechanism.
3Use of energy by moving object
If a single PLL with integer divider is used, then power consumption is reduced, but the ability to generate non-integer related frequencies is limited
Solution Approach 1:
The patent changes the division parameter from integer-only to fractional values. By introducing a fractional divider that can divide by non-integer values (e.g., 2.5, 3.75), the system can generate frequencies that are not integer-related. This parameter change enables a single PLL to replace multiple PLLs, as the fractional division ratio provides the necessary frequency flexibility without requiring additional PLL circuits, thus maintaining low power consumption while improving frequency generation capability.
Data Source
AI summary
A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ΣΔ modulator and a summer to utilize an input N.α control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or β value of the full quadrant analog interpolator.