Fractional Clock Divider Dithering for Spur Suppression
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Solution Overview
Problem
Multifunctional integrated circuits (ICs) face challenges in supporting multiple sampling rates and clock frequencies, leading to coupling spurs and degradation of spurious free dynamic range (SFDR) due to digital activity coupling with analog activity, particularly when implementing fractional clock division.
Innovation Solution
A method for dithering a fractional clock divider is introduced, involving the generation of clock enable sequences through a cyclic rotation of a seed pattern, using a cyclic shift register and selector logic circuit, or a kQ modulo N counter, to distribute low frequency digital activity randomly across high frequency clock edges, effectively eliminating low frequency clock spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock frequencies are implemented in a multifunctional IC, then the IC can support multiple sampling rates and interface rates, but coupling spurs are generated due to digital activity coupling with analog activity
Solution Approach 1:
The patent applies dynamics by making the clock division ratio variable rather than fixed. The clock divider dynamically changes its division ratio based on control signals, allowing the same hardware to support multiple sampling rates and interface rates. This dynamic reconfiguration enables the IC to adapt to different operating conditions while maintaining proper clock synchronization and minimizing coupling spurs through controlled clock distribution.
Solution Approach 2:
The patent implements a universal clock divider circuit that can serve multiple functions and support various clock frequencies. The clock divider is designed to be reconfigurable, allowing a single circuit to replace multiple dedicated clock divider circuits. This multi-functionality reduces the overall number of clock dividers needed in the IC while maintaining the ability to support multiple sampling rates and interface rates.
2Device complexity
If digital logic runs at a fixed low frequency, then the clock division is simple, but interleaving spurs appear due to regular digital activity patterns
Solution Approach 1:
The patent introduces dynamics by varying the clock division ratio over time rather than maintaining a fixed ratio. The clock divider dynamically adjusts its division factor based on control signals, which randomizes the timing of digital activity patterns. This dynamic variation eliminates the regular interleaving spurs that would occur with a fixed division ratio, while still maintaining a relatively simple clock division architecture.
3Object-generated harmful factors
If brute force dithering is used to eliminate spurs, then coupling spurs are reduced, but the number of required clock dividers increases
Solution Approach 1:
The patent implements a universal, reconfigurable clock divider that can perform multiple clock division functions with a single circuit. This multi-functional design eliminates the need for multiple separate clock divider circuits that would be required in a brute force dithering approach. The single clock divider can be dynamically reconfigured to provide different division ratios and dithering patterns, reducing the overall number of clock dividers needed in the IC.
Solution Approach 2:
The patent merges the functions of multiple clock dividers into a single reconfigurable clock divider circuit. By combining the dithering functionality, multiple division ratios, and multiple output clock generation into one unified circuit, the patent reduces the total number of clock dividers required while maintaining the ability to eliminate coupling spurs through dithered clock division.
Data Source
AI summary
A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.