Fractional Clock Divider with Glitchless Phase-Shift Output
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Solution Overview
Problem
Existing digital circuits face difficulty in dividing a clock by a non-integer number, as seen in applications like 10 G Ethernet transceivers, where dividing a 5.15625 GHz clock by 16.5 is necessary to obtain a 312.5 MHz clock, which is more challenging than dividing by an integer.
Innovation Solution
A fractional divider circuit that shifts the clock's phase by P/Qth of a period, where N, P, and Q are integers, effectively increasing the clock's period by N+(P/Q) to achieve division by N+(P/Q), using a digital divider circuit and phase shifting techniques, and masking glitches to prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital circuit divides a clock by a non-integer number, then the clock frequency can be precisely adjusted for applications like 10 G Ethernet transceivers, but the circuit complexity increases significantly compared to integer division
Solution Approach 1:
The patent segments the non-integer division operation into two separate integer division operations. A first counter divides the input clock by N (integer part), and a second counter divides by Q (denominator of fractional part). This segmentation allows the complex non-integer division to be implemented using standard integer division circuits, reducing overall complexity while maintaining precision.
Solution Approach 2:
The patent introduces an intermediary mechanism using two separate counters (first counter for N and second counter for Q) that work together to achieve non-integer division. The output of the first counter is further divided by the second counter, creating an intermediate step that enables precise non-integer frequency division without requiring a completely new complex circuit design.
2Measurement precision
If phase shifting is used to achieve non-integer clock division, then accurate frequency division is achieved, but glitches are introduced in the output signal
Solution Approach 1:
The patent extracts the problematic phase shifting operation from the clock division process. Instead of shifting the input clock phase, the patent uses two separate counters that naturally produce clean digital outputs. The fractional division is achieved through the combination of these two counters rather than through phase manipulation, thereby eliminating glitch generation.
Solution Approach 2:
The patent converts the potential harm of glitches into a benefit by using the natural overflow and reset behavior of digital counters. The first counter divides by N and the second by Q, and their combined operation naturally produces the desired N+(P/Q) division ratio using clean digital transitions, turning what would have been a glitch-prone phase shift into a clean digital counting operation.
3Device complexity
If a counter is used to divide a clock by an integer, then the circuit is simple and well-known, but it cannot divide by non-integer numbers required in applications like 10 G Ethernet transceivers
Solution Approach 1:
The patent creates a universal divider circuit that can handle both integer and non-integer division ratios. By using two counters with programmable values N and Q, the circuit becomes multi-functional - it can divide by any integer N, any integer Q, and any non-integer ratio N+(P/Q). This universal design maintains the simplicity of standard digital counters while greatly expanding the division ratio flexibility needed for various clock frequency requirements.
Data Source
AI summary
A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.