Fractional Clock Divider for Low-EMI and Low-Jitter Clocking
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Solution Overview
Problem
Existing electronic devices face challenges in reducing electromagnetic emission while maintaining clock signal integrity, particularly in sensitive environments, as traditional spread-spectrum clock generators are not compatible with jitter-sensitive communication interfaces, leading to the need for additional costly clock generator circuits.
Innovation Solution
A fractional clock divider and jitter generator system that uses a pseudo-random number generator to dynamically adjust the divisor of a clock signal, creating a spread-spectrum clock signal with reduced electromagnetic emission and a narrow-band clock signal suitable for jitter-sensitive peripherals from a single source clock signal, thereby reducing the need for separate clock generator circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If spread-spectrum clock signal generation is used to reduce electromagnetic emission, then electromagnetic emission is reduced, but compatibility with jitter-sensitive communication interfaces deteriorates
Solution Approach 1:
The patent segments the clock signal generation into two distinct paths: a spread-spectrum path for reducing electromagnetic emission and a narrow-band path for jitter-sensitive interfaces. The single source clock signal is divided, with one branch undergoing spread-spectrum modulation and the other remaining unmodulated, allowing both requirements to be satisfied simultaneously without interference.
Solution Approach 2:
The patent creates a multi-functional clock signal generation system where a single source clock signal serves multiple purposes: generating both spread-spectrum clock signals for electromagnetic emission reduction and narrow-band clock signals for jitter-sensitive communication interfaces. This universal approach eliminates the need for separate clock generators for different interface types.
2Adaptability or versatility
If additional narrow-band clock generator circuits are added to support jitter-sensitive interfaces, then compatibility with jitter-sensitive interfaces is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the functions of multiple clock generators into a single integrated system. Instead of having separate spread-spectrum clock generators and narrow-band clock generators, the invention combines them into one unified circuit that processes a single source clock signal to produce both types of output signals, thereby reducing overall device complexity.
Solution Approach 2:
The unified clock signal generation circuit performs multiple functions: it generates both spread-spectrum and narrow-band clock signals from a single source, supporting both electromagnetic emission reduction and jitter-sensitive interface requirements without needing additional dedicated circuits for each function.
3Adaptability or versatility
If additional clock generator circuits are implemented to support both spread-spectrum and narrow-band requirements, then adaptability is improved, but die area and power consumption increase
Solution Approach 1:
The patent combines multiple clock generation functions into a single power-efficient circuit. By merging the spread-spectrum modulation function and the narrow-band signal generation function into one unified circuit processing a single source clock signal, the total power consumption is reduced compared to running multiple separate clock generators simultaneously.
Solution Approach 2:
The unified clock signal generation circuit provides universal support for both spread-spectrum and narrow-band interfaces while consuming less power than multiple dedicated circuits would require. The single source clock signal is efficiently distributed and processed to meet multiple interface requirements without redundant power consumption.
Data Source
AI summary
The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor D(t) represented by the mixed divisor signal.