Fractional Clock Divider Using Phase-Shifted Signal Selection
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Solution Overview
Problem
Existing electronic circuits struggle to generate an output signal with a frequency that is a non-integer fraction of the input signal, such as dividing a 480 MHz clock signal by 12/13, which is not efficiently addressed by conventional integer division methods.
Innovation Solution
The solution involves generating multiple phase-shifted signals with a phase difference of F times the time period of the input signal, using a selection circuit to select specific phase-shifted signals in each cycle, and a counter to count state changes, allowing for division by a non-integer fraction M+F, where M is an integer and F is a fraction represented as Q/R, with R intermediate signals being phase-shifted equally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional integer division methods are used, then the circuit design is simple, but non-integer frequency division cannot be achieved
Solution Approach 1:
The patent segments the frequency division operation into two parts: an integer division component (M) and a fractional division component (F=Q/R). The counter is divided into a main counter that counts up to M and a fractional counter that handles the Q/R portion. This segmentation allows the circuit to achieve non-integer division capability while maintaining relatively simple circuit architecture by reusing existing counter infrastructure.
Solution Approach 2:
The patent introduces dynamic switching between different counting modes. The counter operates in normal counting mode for M cycles and then switches to a special mode to handle the fractional Q/R portion. This dynamic operation allows the same hardware to adaptively perform both integer and fractional division functions, achieving versatility without proportionally increasing complexity.
2Measurement precision
If non-integer frequency division is implemented, then frequency precision is improved, but jitter increases
Solution Approach 1:
The patent employs feedback mechanisms where the counter output feeds back to control the phase shifter and frequency shifter. The fractional counter's output (Q/R) provides feedback that adjusts the phase and frequency of the intermediate signal. This closed-loop feedback ensures that the non-integer division is achieved with high precision while maintaining signal stability by continuously correcting any deviations.
Solution Approach 2:
The patent changes multiple parameters dynamically: phase shift amount, frequency shift amount, and counting values. By adjusting these parameters in coordination - shifting phase by a first amount, shifting frequency by a second amount, and using different counting values in different cycles - the system achieves precise non-integer frequency division while managing jitter through coordinated parameter modulation rather than isolated changes.
3Measurement precision
If phase and frequency shifting are applied, then non-integer division accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic switching between different operating states. The phase shifter and frequency shifter are activated only during specific cycles when needed for fractional division, rather than operating continuously. The counter alternates between normal counting cycles and fractional adjustment cycles. This periodic action reduces average power consumption while maintaining division accuracy by applying shifting operations only when necessary.
Solution Approach 2:
The patent discards the continuous operation of phase and frequency shifters, activating them only during the fractional Q/R portion of the division cycle. During the main M-counting cycles, these components remain inactive or in a low-power state. The system recovers full precision during the brief fractional adjustment periods, achieving accurate non-integer division with reduced overall power consumption by limiting active shifting to only when needed.
Data Source
AI summary
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.