Fractional Clock Divider Using Dual-Edge One-Shot Pulses
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Solution Overview
Problem
Phase-locked-loop clock generation systems for digital integrated circuits lack flexibility in divide ratios, limiting their ability to lock to a wide range of reference frequencies and potentially requiring faster local oscillator operation.
Innovation Solution
A frequency divider unit with a digital frequency divider configured to divide by odd integers and a dual-edge-triggered one-shot to double the output frequency, allowing for configurable divide ratios including non-integer values like 1.5, 2.5, and 3.5, and integer ratios, with pulsewidth determination from circuit delays or clock signals, enabling greater flexibility in frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional frequency dividers with fixed integer divide ratios are used, then the circuit design is simple, but the system lacks flexibility in locking to different reference frequencies
Solution Approach 1:
The patent implements dynamic divide ratios by using a dual-edge-triggered one-shot circuit that can operate in different modes (single-edge and dual-edge triggering). This allows the frequency divider to adaptively change its division behavior based on control signals, enabling non-integer divide ratios (e.g., 1.5, 2.5, 3.5) while maintaining a relatively simple circuit structure. The dynamic switching between triggering modes provides the needed flexibility without requiring completely separate circuits for each divide ratio.
2Adaptability or versatility
If the local oscillator operates at higher frequencies to cover a wider range, then the frequency range is extended, but the power consumption and circuit stress increase
Solution Approach 1:
The patent changes the operational parameters of the frequency divider by introducing non-integer divide ratios through the dual-edge-triggered one-shot circuit. This allows the system to achieve a wider range of output frequencies by varying the divide ratio parameter rather than increasing the local oscillator frequency. For example, dividing by 1.5, 2.5, or 3.5 provides intermediate frequency steps that expand the usable frequency range while keeping the local oscillator operating at moderate, power-efficient frequencies.
3Speed
If the local oscillator operates at higher frequencies to achieve faster switching, then the switching speed is improved, but the reliability and stability decrease
Solution Approach 1:
The patent uses dynamic control of the one-shot circuit to achieve fast effective switching without requiring the local oscillator to run at high frequencies. The dual-edge-triggered one-shot can rapidly switch between different divide ratio modes in response to phase detector output, providing fast response and effective switching speed improvement while the local oscillator itself operates at stable, lower frequencies that ensure circuit reliability.
Data Source
AI summary
A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.