Fractional Clock Divider Using Phase-Shifted Clocks for RF Noise Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation circuits in transmitters and receivers are sensitive to noise at fundamental RF frequencies and harmonics, necessitating the operation of other circuitry at frequencies different from these, which is not effectively addressed by current clock division methods.
Innovation Solution
A communication circuit with a clock divider circuit that generates an output clock signal with a fundamental frequency divided by a factor of (2N+1)/2N, producing 2N+1 pre-aligned phase-shifted clock signals and 2N unique phase-shifted clock signals, allowing for efficient noise reduction by operating at non-integer fractions of the input clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional integer division clock circuits are used, then the circuit structure is simple, but the noise sensitivity at fundamental RF frequencies and harmonics cannot be effectively reduced
Solution Approach 1:
The clock division function is segmented into multiple independent modules: a divide-by-(2N+1) circuit that generates 2N+1 phase-shifted clock signals, a phase selection circuit that selects 2N signals, and a multiply-by-2N/2 circuit. This segmentation allows the system to achieve fractional division while maintaining modular complexity and enabling effective noise reduction through frequency diversification.
Solution Approach 2:
The circuit dynamically selects and combines multiple phase-shifted clock signals based on the fractional division requirement. The phase selection circuit dynamically chooses 2N out of 2N+1 available signals, and the multiply-by-2N/2 circuit dynamically combines them to produce the final output frequency of f_in × 2N/(2N+1), adapting to different division ratios while avoiding fixed frequency harmonics.
2Object-affected harmful factors
If the output clock frequency is set to non-integer fractions of input frequency, then noise interference is reduced, but the clock division ratio becomes more complex
Solution Approach 1:
The circuit changes the frequency parameter from integer division to fractional division by a fixed factor of 2N/(2N+1). The divide-by-(2N+1) circuit generates signals at frequency f_in/(2N+1), which are then combined and doubled to achieve the target frequency f_in × 2N/(2N+1). This parameter transformation effectively moves the operating frequency away from harmful harmonic multiples of the input clock.
Solution Approach 2:
The solution introduces a new dimensional approach by using phase domain operations instead of simple frequency division. By generating 2N+1 phase-shifted signals and selectively combining 2N of them through the multiply-by-2N/2 circuit, the system achieves fractional frequency multiplication in a different operational dimension, simplifying the overall division ratio implementation.
Data Source
AI summary
A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.