Fractional Clock Divider for Asymmetric Image Splitter Outputs
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Solution Overview
Problem
Current Gigabit Multimedia Serial Link (GMSL) serializer and deserializer systems require phase lock loop (PLL) oscillators to generate video clocks for asymmetric image splitters, which increase power consumption, size, and cost, especially as the number of displays in vehicles increases, necessitating a solution that eliminates the need for PLLs.
Innovation Solution
Implementing a fractional clock divider circuit with a one-bit sigma-delta modulator and digital proportional error feedback control loop to generate compatible display clock frequencies for individual displays from a single super video stream, allowing for asymmetric image splitting without the use of PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL oscillators are used to generate video clocks for asymmetric image splitters, then reliable clock generation is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the PLL oscillator component from the system by implementing a fractional clock divider circuit that generates the required video clocks directly from the input clock signal, thereby eliminating the power consumption associated with PLL operation while maintaining clock generation functionality
Solution Approach 2:
The patent creates a simplified copy of the clock generation function using a fractional clock divider that replicates the essential timing functionality of PLLs without requiring the complex feedback mechanisms and high power consumption of traditional phase-locked loop circuits
2Reliability
If PLL oscillators are used to generate video clocks for asymmetric image splitters, then reliable clock generation is achieved, but device size increases
Solution Approach 1:
The patent removes the PLL oscillator block from the device architecture and replaces it with a compact fractional clock divider implementation that achieves the same clock generation purpose with significantly reduced area footprint
Solution Approach 2:
The patent employs a simpler, less expensive clock division approach that sacrifices the high-performance feedback control of PLLs in favor of a more area-efficient structure suitable for the specific application requirements of asymmetric image splitting
3Reliability
If PLL oscillators are used to generate video clocks for asymmetric image splitters, then reliable clock generation is achieved, but cost increases
Solution Approach 1:
The patent extracts the expensive PLL oscillator component and replaces it with a fractional clock divider that can be implemented using standard digital logic cells, significantly reducing bill of materials cost and simplifying the manufacturing process
Solution Approach 2:
The patent adopts a cost-effective clock generation approach using simple digital division logic rather than expensive analog PLL circuits, making the overall system more economical while meeting the functional requirements of asymmetric image splitting
4Adaptability or versatility
If multiple displays are supported with different resolutions, then system versatility is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal fractional clock divider circuit that can accommodate multiple display resolutions and configurations through programmable division ratios, allowing a single circuit to serve multiple functions without requiring separate clock generation paths for each display type
Solution Approach 2:
The patent achieves display versatility by dynamically changing the clock division parameters (N and M values) rather than requiring different hardware configurations, allowing the same circuit to adapt to various display resolutions and timing requirements through simple parameter adjustment
Data Source
AI summary
Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.