Fractional Clock Synthesizer Using Dual-Edge Period Modulation
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Solution Overview
Problem
Existing digital techniques for generating and modulating clock or carrier waveforms suffer from poor timing stability and require increased input clock frequency for improved timing resolution, which is undesirable.
Innovation Solution
A digital fractional clock synthesizer with period modulation that uses a phase decrementer, clock generator, clock phase selector, and phase generator and combiner to generate an output clock from both rising and falling edges of a single-phase or multi-phase clock, allowing for arbitrary period modulation without increasing the input clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integer division by a counter utilizing either rising or falling edges is used, then the device complexity is reduced, but the timing resolution deteriorates
Solution Approach 1:
The counter is segmented into two independent counters: a rising-edge counter that counts on rising edges and a falling-edge counter that counts on falling edges. This segmentation allows both counters to operate simultaneously and contribute to timing resolution without increasing overall device complexity, as each counter remains relatively simple in structure.
Solution Approach 2:
The invention transitions from using a single counter dimension (either rising or falling edges) to utilizing two counter dimensions simultaneously (both rising and falling edges). This dimensional expansion doubles the effective timing resolution capability without proportionally increasing device complexity, as the additional counter operates independently and parallel to the first.
2Measurement precision
If input clock frequency is increased to achieve improved timing resolution, then the timing resolution is improved, but the use of energy increases
Solution Approach 1:
The invention changes the parameter of clock edge utilization from single-edge (rising or falling) to dual-edge (both rising and falling) counting. This parameter change effectively doubles the timing resolution for the same input clock frequency, eliminating the need to increase clock frequency and thereby avoiding the associated increase in energy consumption.
3Device complexity
If a single counter utilizing one edge is used, then the device complexity is reduced, but the timing stability deteriorates
Solution Approach 1:
The timing measurement function is segmented into two independent counting operations: one for rising edges and one for falling edges. This segmentation allows the system to utilize both edges for timing measurement, improving timing stability through redundant measurement paths while keeping each individual counter structure simple.
Solution Approach 2:
The system implements feedback by using the output of both rising-edge and falling-edge counters to jointly determine the timing measurement result. This feedback mechanism allows the system to cross-validate timing measurements from both edge types, improving timing stability and reliability without requiring complex individual counter structures.
Data Source
AI summary
An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.