Fractional Clock Generation Using Alternating Integer Dividers
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Solution Overview
Problem
Existing locked loop circuits, such as phase-locked loops, face challenges in generating fractional clock signals with small frequency steps due to the impracticality of large frequency dividers, which can lead to instability and increased jitter.
Innovation Solution
A fractional locked loop circuit that combines two periodic clock signals with different frequencies, using a multiplexer to switch between them based on a select signal, allowing for the generation of desired frequency steps without the need for extremely large frequency dividers, thereby minimizing jitter and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large frequency dividers are used to generate fractional clock signals with small frequency steps, then frequency precision is improved, but circuit stability deteriorates and jitter increases
Solution Approach 1:
The patent divides the frequency division function into two separate integer frequency dividers working in alternating periods, rather than using one large fractional frequency divider. This segmentation allows each divider to operate with smaller division ratios, improving stability while achieving fractional frequency steps through temporal multiplexing.
Solution Approach 2:
The patent employs periodic switching between two different integer frequency division ratios (N1 and N2) over alternating periods. By alternating between these two integer dividers, the system achieves an average fractional frequency division ratio without requiring a single large fractional divider, thus maintaining circuit stability.
2Measurement precision
If large frequency dividers are used to achieve small frequency steps, then frequency step precision is improved, but device area increases
Solution Approach 1:
The frequency division function is segmented into two separate integer frequency dividers with smaller division ratios, rather than one large fractional frequency divider. This reduces the layout area required while achieving the same fractional frequency precision through alternating operation.
Solution Approach 2:
The patent uses two copies of integer frequency divider circuits with relatively small division ratios, alternating between them to achieve fractional frequency division. This approach requires less total area than a single large fractional frequency divider while maintaining frequency precision.
3Measurement precision
If large frequency dividers are used to generate fractional clock signals, then frequency control precision is improved, but phase noise and jitter increase
Solution Approach 1:
The patent segments the frequency control function into two integer frequency dividers with smaller division ratios, reducing the phase noise and jitter associated with large fractional dividers while maintaining frequency control precision through alternating operation.
Data Source
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AI summary
A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.