Adaptive Fractional-N Clock Divider Control for Jitter and Spur Reduction
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Solution Overview
Problem
Clock synthesizers using phase-locked loops with fractional-N dividers suffer from jitter and spurs in the output clock signal, leading to performance limitations and data loss, necessitating a low-noise, flexible solution.
Innovation Solution
An adaptive clock synthesizer apparatus and method that employs a frequency divider with an adjustable control signal, utilizing a measurement circuit to provide digital time information for approximating a fractional divide ratio, and an adaptive adjustment circuit to generate an adjusted frequency divider control signal, which reduces spurs and jitter by interpolating between delayed versions of the feedback clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N feedback divider is used in the PLL to achieve flexible frequency synthesis, then the adaptability and frequency range are improved, but jitter and spurs are introduced in the output clock signal
Solution Approach 1:
A time-to-digital converter (TDC) is introduced as an intermediary component to measure the timing error between the actual feedback clock signal and the ideal feedback clock signal. This TDC converts the timing difference into a digital value that can be processed by the adjustment circuit to generate compensation signals, thereby eliminating jitter and spurs while maintaining fractional-N division flexibility.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the time-to-digital converter is fed back to the adjustment circuit, which then adjusts the feedback divider control signal. This closed-loop feedback system continuously measures and corrects timing errors, reducing jitter and spurs in the output clock signal while maintaining the flexible frequency synthesis capability of the fractional-N divider.
2Reliability
If the PLL loop bandwidth is increased to reduce jitter, then the noise filtering capability is improved, but spurs and instability increase
Solution Approach 1:
The patent segments the jitter reduction function from the frequency synthesis function by introducing a separate time-to-digital converter and adjustment circuit. This allows the PLL to maintain a wider loop bandwidth for better noise filtering while the separate adjustment circuit handles spur reduction through precise timing correction, eliminating the traditional trade-off between jitter reduction and spur generation.
Solution Approach 2:
The patent replaces the traditional mechanical/analog approach of adjusting PLL loop bandwidth to reduce jitter with a digital timing measurement and correction system. The time-to-digital converter and adjustment circuit use digital signal processing to reduce jitter and spurs independently, allowing the PLL loop bandwidth to be optimized for noise filtering without the harmful side effects of increased spurs and instability.
3Device complexity
If a first-order sigma-delta modulator is used to generate the divide sequence, then the device complexity is reduced, but quantization noise and spurs increase
Solution Approach 1:
The patent introduces a time-to-digital converter as an intermediary between the sigma-delta modulator and the feedback divider. This TDC measures the actual timing error caused by quantization noise and provides correction information to the adjustment circuit, which then compensates for spurs and quantization noise without requiring a more complex modulator architecture.
Solution Approach 2:
The patent converts the harmful quantization noise and spurs generated by the simple first-order sigma-delta modulator into measurable timing errors that can be corrected. The time-to-digital converter captures these errors, and the adjustment circuit uses them to generate compensation signals, effectively transforming the modulator's deficiencies into correctable data that improves the overall output quality.
Data Source
AI summary
An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.