Fractional Clock Division Circuit With Phase Difference Control
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Solution Overview
Problem
Conventional methods for frequency division of clock pulse signals in semiconductor integrated circuits are limited to integral frequency division and fail to achieve fractional frequency division effectively, leading to phase differences that can cause circuit malfunction, especially when attempting to generate clock signals with non-integer division ratios like 6.5.
Innovation Solution
A semiconductor integrated circuit design that includes a clock control unit to generate a gated clock signal by masking the input clock signal at predetermined timings, allowing for fractional frequency division by adjusting the counting operation and using registers to set values A, B, and C, which enables the division of the input clock signal by A+C/B, thereby minimizing phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a prescaler is used to divide the high-speed clock signal to generate a clock source signal for the frequency division counter, then the circuit size is reduced, but the cycle of the generated clock signal varies and a large phase difference occurs between the generated clock signal and the ideal clock signal
Solution Approach 1:
The patent introduces a phase adjustment circuit as an intermediary component between the frequency division counter and the output. This circuit includes a phase adjustment register that can selectively delay the output clock signal by a predetermined period (e.g., one cycle of the high-speed clock signal) to compensate for the phase difference caused by the prescaler, thereby aligning the generated clock signal with the ideal clock signal timing
Solution Approach 2:
The patent changes the timing parameter of the output clock signal by introducing a controllable delay mechanism. The phase adjustment register can set different delay periods to optimize the phase alignment between the generated clock signal and the ideal clock signal, allowing the system to adapt to different frequency division ratios and prescaler configurations
2Measurement precision
If fractional frequency division is implemented by switching the number of frequency division between N and N+1, then the desired clock cycle is approximated, but the phase difference between the generated clock signal and the ideal clock signal becomes large
Solution Approach 1:
The phase adjustment circuit acts as a mediator that compensates for the phase errors introduced by fractional frequency division switching. By selectively delaying the output signal based on the current division ratio being used (N or N+1), the circuit ensures that the phase relationship between the generated and ideal clock signals is maintained within acceptable limits
Solution Approach 2:
The patent implements dynamic phase adjustment that adapts to the current operating mode. When the frequency division counter switches between N and N+1 division ratios, the phase adjustment register dynamically adjusts the delay period to compensate for the different phase characteristics introduced by each division ratio, ensuring continuous phase alignment
3Adaptability or versatility
If multiple clock oscillators are provided to generate different clock pulse signals for different circuits, then each circuit receives appropriate clock signals, but the circuit size increases
Solution Approach 1:
The patent implements a universal clock generation system where a single high-speed clock oscillator serves multiple circuits through frequency division. The frequency division counter can be configured with different division ratios (N, N+1) and the phase adjustment circuit can adapt its delay period, allowing the same hardware to generate multiple different clock signals suitable for different circuit requirements without needing separate oscillators for each circuit
Data Source
AI summary
Disclosed is a semiconductor integrated circuit for generating a frequency division clock signal that approximates a desired clock signal without increasing a size thereof. The semiconductor integrated circuit masks, for each programmable cycle, a clock signal to be supplied to a transmission clock generation unit 100, thereby delaying a counting operation of a clock counter 101, and setting a timing for extending a transmission clock signal so as to cause a transmission rate of an average frequency of the transmission clock signal to approximate a predetermined transmission rate, wherein the transmission clock generation unit 100 divides a frequency of a clock source signal S301 that is a high-speed clock signal.