Fractional Clock Generator Using Phase Interpolation for Low Noise
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Solution Overview
Problem
Conventional clock generators, such as phase-locked loops (PLL) and frequency synthesizers, face challenges in reducing noise and power consumption, especially when generating signals with high resolution, leading to increased manufacturing costs and noise quality degradation.
Innovation Solution
A fractional-division clock generator is developed, incorporating a delta-sigma modulation (DSM) for generating division and phase control signals, an adjustable frequency divider, and a phase interpolator (PI) to perform fractional division operations, which reduces power consumption and noise by operating at lower frequencies and utilizing phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency synthesizer uses DSM to generate fractional division signals, then the output frequency resolution is improved, but quantization noise increases and loop filter area increases
Solution Approach 1:
The patent segments the frequency division process into two independent stages: integer division by the frequency divider and fractional phase adjustment by the phase interpolator. This segmentation allows the system to achieve fractional frequency resolution without using DSM, thereby eliminating quantization noise from the frequency synthesis process while maintaining high frequency resolution through the combination of integer division ratios and phase interpolation factors.
Solution Approach 2:
The phase interpolator acts as an intermediary component that receives the divided signal from the frequency divider and applies fractional phase adjustment to achieve the final output frequency. This intermediary approach replaces the direct fractional division method and avoids the quantization noise inherent in DSM-based frequency synthesis.
2Object-generated harmful factors
If the loop filter bandwidth is reduced to suppress quantization noise, then noise is reduced, but the area of the loop filter increases
Solution Approach 1:
The patent extracts the noise suppression function from the loop filter by eliminating the source of quantization noise through the removal of DSM. Since the frequency synthesis no longer relies on DSM for fractional division, the loop filter does not need to suppress quantization noise, allowing for a smaller filter area while maintaining low noise performance.
3Measurement precision
If the number of output phases from VCO is increased to achieve high resolution, then frequency resolution is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency resolution adjustment by allowing the system to vary the division ratio of the frequency divider and the phase interpolation factor of the phase interpolator based on different output frequency requirements. This dynamic approach enables high frequency resolution without requiring a fixed large number of VCO output phases, thereby reducing power consumption while maintaining the ability to achieve high resolution when needed.
Data Source
AI summary
A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.