Fractional Clock Generation Using Phase Selection for Low Jitter
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Solution Overview
Problem
Existing systems for generating fractional clock signals face challenges in achieving low power consumption, small die area, and low jitter performance, especially when dealing with non-integer frequency division, as they often require complex circuits and additional components that increase noise and power consumption.
Innovation Solution
A fractional clock generator that uses a phase generator to produce multiple clock signals of varying phases, which are then selected by a multiplexer within a feedback loop to adjust the output frequency, allowing for non-integer frequency division with a single voltage-controlled oscillator and minimizing the need for separate PLLs and additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate PLLs are used to generate each clock signal for non-integer frequency ratios, then frequency generation capability is improved, but die area and power consumption increase
Solution Approach 1:
The patent combines multiple PLL functions into a single PLL by using a phase generator that creates multiple phase-shifted clock signals from one VCO. These phased signals are then selectively combined through a multiplexer controlled by a state machine, allowing the single PLL to generate multiple clock frequencies including non-integer ratios, thereby reducing die area while maintaining frequency generation capability
Solution Approach 2:
The single PLL is designed to perform multiple functions by generating a base clock signal that is then phase-generated and selectively multiplexed to produce various output frequencies. The system can generate both integer and non-integer frequency ratios using the same hardware infrastructure, making the PLL universal for different clock generation requirements
2Adaptability or versatility
If multiple PLLs are used to generate each clock signal, then frequency generation capability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple PLL power-consuming components into a single PLL by using phase generation and multiplexing techniques. One VCO and one PLL circuit generate all required clock signals through phase manipulation and selective combination, significantly reducing the total power consumption compared to using separate PLLs for each frequency
Solution Approach 2:
The system uses periodic phase shifting and multiplexing of clock signals to generate different output frequencies. By periodically selecting different phase-shifted versions of the base clock signal through a state-controlled multiplexer, the system achieves multiple frequency outputs from a single power-efficient PLL
3Adaptability or versatility
If additional components are added to achieve fractional frequency division, then frequency ratio capability is improved, but jitter performance deteriorates
Solution Approach 1:
The phase generator pre-generates multiple phase-shifted versions of the base clock signal before they are needed for output. By having all phase variations already available and synchronized from the same VCO, the system eliminates jitter that would be introduced by real-time frequency multiplication or division operations, maintaining low jitter while achieving fractional frequency ratios
Data Source
AI summary
Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.